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參數(shù)資料
| 型號(hào)： | MM74HC123ASJ |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 諧振器 |
| 英文描述： | Dual Retriggerable Monostable Multivibrator |
| 中文描述： | HC/UH SERIES, DUAL MONOSTABLE MULTIVIBRATOR, PDSO16 |
| 封裝： | 5.30 MM, EIAJ TYPE2, SOP-16 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 116K |
| 代理商： | MM74HC123ASJ |
5
www.fairchildsemi.com
M
Theory of Operation
1POSITIVE EDGE TRIGGER
2NEGATIVE EDGE TRIGGER
3POSITIVE EDGE TRIGGER
4POSITIVE EDGE RE-TRIGGER (PULSE LENGTHENING)
5RESET PULSE SHORTENING
6CLEAR TRIGGER
FIGURE 1.
TRIGGER OPERATION
As shown in Figure 1and the logic diagram, before an
input trigger occurs, the one shot is in the quiescent state
with the Q output LOW, and the timing capacitor C
EXT
com-
pletely charged to V
CC
. When the trigger input A goes from
V
CC
to GND (while inputs B and clear are held to V
CC
) a
valid trigger is recognized, which turns on comparator C1
and Nchannel transistor N11. At the same time the output
latch is set. With transistor N1 on, the capacitor C
EXT
rap-
idly discharges toward GND until V
REF1
is reached. At this
point the output of comparator C1 changes state and tran-
sistor N1 turns off. Comparator C1 then turns off while at
the same time comparator C2 turns on. With transistor N1
off, the capacitor C
EXT
begins to charge through the timing
resistor, R
EXT
, toward V
CC
. When the voltage across C
EXT
equals V
REF2
, comparator C2 changes state causing the
output latch to reset (Q goes LOW) while at the same time
disabling comparator C2. This ends the timing cycle with
the monostable in the quiescent state, waiting for the next
trigger.
A valid trigger is also recognized when trigger input B goes
from GND to V
CC
(while input A is at GND and input clear
is at V
CC
2). The MM74HC123A can also be triggered when
clear goes from GND to V
CC
(while A is at GND and B is at
V
CC
6).
It should be noted that in the quiescent state C
EXT
is fully
charged to V
CC
causing the current through resistor R
EXT
to be zero. Both comparators are “off” with the total device
current due only to reverse junction leakages. An added
feature of the MM74HC123A is that the output latch is set
via the input trigger without regard to the capacitor voltage.
Thus, propagation delay from trigger to Q is independent of
the value of C
EXT
, R
EXT
, or the duty cycle of the input
waveform.
RETRIGGER OPERATION
The MM74HC123A is retriggered if a valid trigger occurs 3
followed by another trigger 4 before the Q output has
returned to the quiescent (zero) state. Any retrigger, after
the timing node voltage at the R/C
EXT
pin has begun to rise
from V
REF1
, but has not yet reached V
REF2
, will cause an
increase in output pulse width T. When a valid retrigger is
initiated 4, the voltage at the R/C
EXT
pin will again drop to
V
REF1
before progressing along the RC charging curve
toward V
CC
. The Q output will remain HIGH until time T,
after the last valid retrigger.
Because the trigger-control circuit flip-flop resets shortly
after C
X
has discharged to the reference voltage of the
lower reference circuit, the minimum retrigger time, t
rr
is a
function of internal propagation delays and the discharge
time of C
X
:
Another removal/retrigger time occurs when a short clear
pulse is used. Upon receipt of a clear, the one shot must
charge the capacitor up to the upper trip point before the
one shot is ready to receive the next trigger. This time is
dependent on the capacitor used and is approximately:
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MM74HC123ASJX | 功能描述:單穩(wěn)態(tài)多諧振蕩器 DualMultivibrator RoHS:否 制造商:Texas Instruments 每芯片元件:1 邏輯系列:LVC 邏輯類型:Monostable Multivibrator 封裝 / 箱體:SSOP-8 傳播延遲時(shí)間:18.6 ns 高電平輸出電流:- 32 mA 低電平輸出電流:32 mA 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| MM74HC125 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:3-STATE Quad Buffers |
| MM74HC125_05 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:3-STATE Quad Buffers |
| MM74HC125J | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MM74HC125J/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-Bit Buffer/Driver |
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