參數(shù)資料
型號: MM74HC273CW
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 鎖存器
英文描述: HC/UH SERIES, OCTAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, UUC
封裝: WAFER
文件頁數(shù): 4/9頁
文件大?。?/td> 115K
代理商: MM74HC273CW
www.fairchildsemi.com
4
MM
74HC273
AC Electrical Characteristics
VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns
AC Electrical Characteristics
CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC
2f
+ I
CC VCC, and the no load dynamic current consumption,
IS = CPD VCC f + ICC.
Symbol
Parameter
Conditions
Typ
Guaranteed
Units
Limit
fMAX
Maximum Operating
50
30
MHz
Frequency
tPHL, tPLH
Maximum Propagation
18
27
ns
Delay, Clock to Output
tPHL
Maximum Propagation
18
27
ns
Delay, Clear to Output
tREM
Minimum Removal Time,
10
20
ns
Clear to Clock
ts
Minimum Setup Time
10
20
ns
Data to Clock
tH
Minimum Hold Time
20
ns
Clock to Data
tW
Minimum Pulse Width
10
16
ns
Clock or Clear
Symbol
Parameter
Conditions
VCC
TA = 25°CTA = 40 to 85°CTA = 55 to 125°C
Units
Typ
Guaranteed Limits
fMAX
Maximum Operating
2.0V
16
5
4
3
MHz
Frequency
4.5V
74
27
21
18
MHz
6.0V
78
31
24
20
MHz
tPHL, tPLH
Maximum Propagation
2.0V
38
135
170
205
ns
Delay, Clock to Output
4.5V
14
27
34
41
ns
6.0V
12
23
29
35
ns
tPHL
Maximum Propagation
2.0V
42
135
170
205
ns
Delay, Clear to Output
4.5V
19
27
34
41
ns
6.0V
18
23
29
35
ns
tREM
Minimum Removal Time
2.0V
0
25
32
37
ns
Clear to Clock
4.5V
0
5
6
7
ns
6.0V
0
4
5
6
ns
ts
Minimum Setup Time
2.0V
26
100
125
150
ns
Data to Clock
4.5V
7
20
25
30
ns
6.0V
5
17
21
25
ns
tH
Minimum Hold Time
2.0V
15
0
ns
Clock to Data
4.5V
60
0
ns
6.0V
40
0
ns
tW
Minimum Pulse Width
2.0V
34
80
100
120
ns
Clock or Clear
4.5V
11
16
20
24
ns
6.0V
10
14
18
20
ns
tr, tf
Maximum Input Rise and
2.0V
1000
ns
Fall Time, Clock
4.5V
500
ns
6.0V
400
ns
tTHL, tTLH
Maximum Output Rise
2.0V
28
75
95
110
ns
and Fall Time
4.5V
11
15
19
22
ns
6.0V
9
13
16
19
ns
CPD
Power Dissipation
(per flip-flop)
45
pF
Capacitance (Note 5)
CIN
Maximum Input
7
10
pF
Capacitance
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