參數(shù)資料
型號(hào): MM74HC589SJ
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: 8-Bit Shift Registers with Input Latches and 3-STATE Serial Output
中文描述: HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16
封裝: 5.30 MM, EIAJ TYPE2, SOP-16
文件頁數(shù): 4/9頁
文件大?。?/td> 89K
代理商: MM74HC589SJ
www.fairchildsemi.com
4
M
AC Electrical Characteristics
V
CC
=
5V, T
A
=
25
°
C, C
L
=
15 pF, t
r
=
t
f
=
6 ns
AC Electrical Characteristics
V
CC
=
2.0
6V, C
L
=
50 pF, t
r
=
t
f
=
6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
30
Units
f
MAX
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PZH
, t
PZL
t
PHZ
, t
PLZ
t
S
t
S
t
S
t
H
t
W
Maximum Operating Frequency for SCK
50
MHz
Maximum Propagation Delay from SCK to Q
H’
Maximum Propagation Delay from SLOAD to Q
H’
Maximum Propagation Delay from LCK to Q
H’
Output Enable Time
30
30
ns
ns
SLOAD
=
logic “0”
R
L
=
1 k
R
L
=
1 k
, C
L
=
5 pF
25
45
ns
18
28
ns
Output Disable Time
Minimum Setup Time from RCK to SCK
Minimum Setup Time from SER to SCK
19
10
10
25
20
20
ns
ns
ns
Minimum Setup Time from Inputs A thru H to RCK
Minimum Hold Time
10
0
20
5
ns
ns
Minimum Pulse Width SCK, RCK, SLOAD
8
16
ns
Symbol
Parameter
Conditions
V
CC
T
A
=
25
°
C
Typ
T
A
=
40 to 85
°
C T
A
=
55 to 125
°
C
Guaranteed Limits
4.8
Units
f
MAX
Maximum Operating
2.0V
6
4
MHz
Frequency for SCK
4.5V
6.0V
2.0V
30
35
175
24
28
220
20
24
265
MHz
MHz
ns
t
PHL
, t
PLH
Maximum Propagation
Delay from SCK or
62
4.5V
6.0V
20
18
35
30
44
37
53
45
ns
ns
SLOAD to Q
H
t
PHL
, t
PLH
Maximum Propagation
Delay from SCK or
2.0V
4.5V
6.0V
120
31
28
225
45
38
280
56
48
340
68
58
ns
ns
ns
C
L
=
150 pF
SLOAD to Q
H
t
PHL
, t
PLH
Maximum Propagation
Delay from RCK to Q
H
2.0V
4.5V
80
25
210
42
265
53
315
63
ns
ns
6.0V
2.0V
4.5V
21
80
25
36
210
52
45
265
66
54
313
77
ns
ns
ns
t
PHL
, t
PLH
Maximum Propagation
Delay RCK to Q
H
C
L
=
150 pF
6.0V
2.0V
4.5V
21
70
22
44
150
30
56
189
38
66
224
45
ns
ns
ns
t
PZH
, t
PZL
Output Enable Time
R
L
=
1 k
6.0V
2.0V
4.5V
20
70
22
26
150
30
32
189
38
38
224
45
ns
ns
ns
t
PHZ
, t
PLZ
Output Disable Time
R
L
=
1 k
6.0V
2.0V
4.5V
20
26
100
20
32
125
25
38
150
30
ns
ns
ns
t
S
Minimum Setup Time
from RCK to SCK
6.0V
2.0V
4.5V
17
100
20
22
125
25
25
150
30
ns
ns
ns
t
S
Minimum Setup Time
from SER to SCK
6.0V
2.0V
4.5V
17
100
20
22
125
25
25
150
30
ns
ns
ns
t
S
Minimum Setup Time
from Inputs A thru H
to RCK
Minimum Hold Time
6.0V
2.0V
4.5V
17
5
5
22
5
5
25
5
5
ns
ns
ns
t
H
5
0
6.0V
2.0V
4.5V
1
5
5
5
ns
ns
ns
t
W
Minimum Pulse Width
30
9
80
16
100
20
120
24
SCK, RCK, SLOAD,
SLOAD
6.0V
8
14
17
20
ns
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