參數(shù)資料
型號(hào): MM74HCT74N
廠商: Fairchild Semiconductor
文件頁(yè)數(shù): 6/10頁(yè)
文件大?。?/td> 0K
描述: IC FLIP FLOP DUAL D-TYPE 14-DIP
標(biāo)準(zhǔn)包裝: 500
系列: 74HCT
功能: 設(shè)置(預(yù)設(shè))和復(fù)位
類(lèi)型: D 型
輸出類(lèi)型: 差分
元件數(shù): 2
每個(gè)元件的位元數(shù): 1
頻率 - 時(shí)鐘: 27MHz
延遲時(shí)間 - 傳輸: 21ns
觸發(fā)器類(lèi)型: 正邊沿
輸出電流高,低: 4.8mA,4.8mA
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 通孔
封裝/外殼: 14-DIP(0.300",7.62mm)
包裝: 管件
1984 Fairchild Semiconductor Corporation
www.fairchildsemi.com
MM74HCT74 Rev. 1.4.0
5
MM74HCT74
Dual
D-T
ype
Flip-Flop
with
Preset
and
Clear
AC Electrical Characteristics
VCC = 5.0V ± 10%, CL = 50 pF, tr = tf = 6ns unless otherwise specified.
Note:
5. CPD determines the no load dynamic power consumption, PD = CPD VCC
2 f + I
CC VCC, and the no load dynamic
current consumption, IS = CPD VCC f + ICC.
Symbol
Parameter
Conditions
TA = 25°C
TA = –40° to +85°C
Units
Typ.
Guaranteed Limits
fMAX
Maximum Operating Frequency
27
21
MHz
tPHL, tPLH
Maximum Propagation Delay from
Clock to Q or Q
21
35
44
ns
tPHL, tPLH
Maximum Propagation Delay from
Preset or Clear to Q or Q
21
35
44
ns
tREM
Minimum Removal Time Preset or
Clear to Clock
20
25
ns
tS
Minimum Setup Time Data to
Clock
20
25
ns
tH
Minimum Hold Time Clock to Data
–3
0
ns
tW
Minimum Pulse Width Clock,
Preset or Clear
916
20
ns
tr, tf
Maximum Clock Input Rise and
Fall Time
500
ns
tTHL, tTLH
Maximum Output Rise and Fall
Time
15
19
ns
CPD
Power Dissipation Capacitance(5)
(per ip-op)
10
pF
CIN
Maximum Input Capacitance
5
10
pF
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