參數(shù)資料
型號(hào): MM908E624
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: Integrated Triple High-Side Switch with Embedded MCU and LIN Serial Communication for Relay Drivers(集成三高端開(kāi)關(guān),帶嵌入式MCU和LIN串行通信功能,用于繼電器驅(qū)動(dòng)器)
中文描述: 綜合三高側(cè)嵌入式微控制器和繼電器驅(qū)動(dòng)器林串行通信(集成三高端開(kāi)關(guān),帶嵌入式微控制器和林串行通信功能,用于繼電器驅(qū)動(dòng)器開(kāi)關(guān))
文件頁(yè)數(shù): 13/24頁(yè)
文件大?。?/td> 718K
代理商: MM908E624
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
908E624
13
DYNAMIC ELECTRICAL CHARACTERISTICS
All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for characteristics of the MCU chip.
Characteristics noted under conditions 9.0 V
V
SUP
16 V, -40
°
C
T
J
125
°
C unless otherwise noted. Typical values noted reflect
the approximate parameter mean at T
A
= 25
°
C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
PHYSICAL LAYER
Driver Characteristics for Normal Slew Rate
(Note 15)
Dominant Propagation Delay Tx to LIN (Measurement Threshold 58.1% V
SUP
)
t
DOM-
min
50
μ
s
Dominant Propagation Delay Tx to LIN (Measurement Threshold 28.4% V
SUP
)
t
DOM-
max
50
μ
s
Recessive Propagation Delay Tx to LIN (Measurement Threshold 42.2% V
SUP
)
t
REC-
min
50
μ
s
Recessive Propagation Delay Tx to LIN (Measurement Threshold 74.4% V
SUP
)
t
REC-
max
50
μ
s
Propagation Delay Symmetry: t
DOM-min
- t
REC-
max
dt1
-10.44
8.12
μ
s
Propagation Delay Symmetry: t
DOM-
max
- t
REC-
min
dt2
-10.44
8.12
μ
s
Driver Characteristics for Slow Slew Rate
(Note 15)
Dominant Propagation Delay Tx to LIN (Measurement Threshold 61.1% V
SUP
)
t
DOM-
min
100
μ
s
Dominant Propagation Delay Tx to LIN (Measurement Threshold 25.1% V
SUP
)
t
DOM-
max
100
μ
s
Recessive Propagation Delay Tx to LIN (Measurement Threshold 38.9% V
SUP
)
t
REC-
min
100
μ
s
Recessive Propagation Delay Tx to LIN (Measurement Threshold 77.8% V
SUP
)
t
REC-
max
100
μ
s
Propagation Delay Symmetry: t
DOM-
min
- t
REC-
max
dt1s
-21.88
17.44
μ
s
Propagation Delay Symmetry: t
DOM-max
- t
REC-
min
dt2s
-21.88
17.44
μ
s
Driver Characteristics for Fast Slew Rate
LIN High Slew Rate (Programming Mode)
SR
FAST
20
V/
μ
s
Receiver Characteristics and Wake-Up Timings
Receiver Dominant Propagation Delay (Note 16)
t
rL
3.5
6.0
μ
s
Receiver Recessive Propagation Delay (Note 16)
t
rH
3.5
6.0
μ
s
Receiver Propagation Delay Symmetry
t
r-Sym
-2.0
2.0
μ
s
Bus Wake-Up Deglitcher
t
propWL
30
50
80
μ
s
Bus Wake-Up Event Reported Note
t
wake
20
μ
s
HIGH-SIDE OUTPUTS HS1 AND HS2
Turn On Time Delay (Note 18)
t
don
10
μ
s
Turn Off Time Delay (Note 18)
t
doff
10
μ
s
Notes
15.
V
SUP
from 7.0 V to 18 V, bus load R0 and C0 1.0 nF/1.0 k, 6.8 nF/660, 10 nf/500. Measurement thresholds: 50% of Tx signal to LIN signal
threshold defined at each parameter.
Measured between LIN signal threshold V
IL
or V
IH
and 50% of Rx signal.
t
wake
is typically 2 internal clock cycles after LIN rising edge detected. Refer to “LIN Bus Wake-Up Behavior” figure. In SLEEP mode the V
DD
rise time is strongly dependant upon the decoupling capacitor at VDD terminal.
Delay between turn on or turn off command and high-side on or high-side off, excluding rise or fall time due to external load.
16.
17.
18.
F
Freescale Semiconductor, Inc.
Go to: www.freescale.com
n
.
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