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參數(shù)資料
| 型號： | MM9S08DV60MLF |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, MS-026BBC, LQFP-64 |
| 文件頁數(shù)： | 6/410頁 |
| 文件大小： | 4299K |
| 代理商： | MM9S08DV60MLF |
Chapter 6 Parallel Input/Output Control
MC9S08DV60 Series Data Sheet, Rev 2
Freescale Semiconductor
103
6.5.5.3
Port E Pull Enable Register (PTEPE)
NOTE
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are congured.
6.5.5.4
Port E Slew Rate Enable Register (PTESE)
Note: Slew rate reset default values may differ between engineering samples and nal production parts. Always initialize slew
rate control to the desired value to ensure correct operation.
76543210
R
PTEPE7
PTEPE6
PTEPE5
PTEPE4
PTEPE3
PTEPE2
PTEPE1
PTEPE0
W
Reset:
00000000
Figure 6-34. Internal Pull Enable for Port E Register (PTEPE)
Table 6-32. PTEPE Register Field Descriptions
Field
Description
7:0
PTEPE[7:0]
Internal Pull Enable for Port E Bits — Each of these control bits determines if the internal pull-up device is
enabled for the associated PTE pin. For port E pins that are congured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port E bit n.
1 Internal pull-up device enabled for port E bit n.
76543210
R
PTESE7
PTESE6
PTESE5
PTESE4
PTESE3
PTESE2
PTESE11
1
PTESE1 has no effect on the input-only PTE1 pin.
PTESE0
W
Reset:
00000000
Figure 6-35. Slew Rate Enable for Port E Register (PTESE)
Table 6-33. PTESE Register Field Descriptions
Field
Description
7:0
PTESE[7:0]
Output Slew Rate Enable for Port E Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTE pin. For port E pins that are congured as inputs, these bits have no effect.
0 Output slew rate control disabled for port E bit n.
1 Output slew rate control enabled for port E bit n.
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