A
d
v
anc
e
I
n
fo
rm
at
io
n
M
C
21
1
4
MM
C
2
1
3
M
C
21
12
—
Rev
.
1.0
350
T
im
e
rM
odu
le
s
(T
IM
1
and
T
IM
2
)
M
O
T
O
R
OLA
Ti
me
rM
odu
le
s
(T
IM
1
a
nd
TI
M
2
)
Table 16-7. Timer Settings and Pin Functions
TIMEN DDR(1) TIMIOS
EDGx
[B:A]
OMx/
OLx(2)
OC3Mx(3)
Pin
Data
Direction
Pin
Driven
by
Pin
Function
Comments
00
X(4)
X
In
Ext.
Digital input
Timer disabled by TIMEN = 0
0
1
X
Out
Data reg.
Digital output
Timer disabled by TIMEN = 0
10
0 (IC)
0 (IC
disabled)
X
0
In
Ext.
Digital input
Input capture disabled by EDGx setting
1
0
X
0
Out
Data reg.
Digital output
Input capture disabled by EDGx setting
1
0
<> 0
X
0
In
Ext.
IC and
digital input
Normal settings for input capture
1
0
<> 0
X
0
Out
Data reg.
Digital output
Input capture of data driven to output pin by CPU
1
0
<> 0
X
1
In
Ext.
IC and
digital input
OC3M setting has no effect because IOS = 0
1
0
<> 0
X
1
Out
Data reg.
Digital output
OC3M setting has no effect because IOS = 0;
input capture of data driven to output pin by CPU
10
1 (OC)
X(3)
0(5)
0
In
Ext.
Digital input
Output compare takes place but does not affect
the pin because of the OMx/OLx setting
1
X
0
Out
Data reg.
Digital output
Output compare takes place but does not affect
the pin because of the OMx/OLx setting
1
0
1
X
<> 0
0
Out
OC action Output compare Pin readable only if DDR = 0(5)
1
X
<> 0
0
Out
OC action Output compare Pin driven by OC action(5)
10
1
X
1
Out
OC
action/
OC3Dx
Output compare
(ch 3)
Pin readable only if DDR = 0(6)
11
1
X
1
Out
OC
action/
OC3Dx
Output
compare/
OC3Dx
(ch 3)
Pin driven by channel OC action and OC3Dx via
channel 3 OC(6)
1. When DDR set the pin as input (0), reading the data register will return the state of the pin. When DDR set the pin as output (1), reading the data
register will return the content of the data latch. Pin conditions such as rising or falling edges can trigger an input capture on a pin configured as an
input.
2. OMx/OLx bit pairs select the output action to be taken as a result of a successful output compare. When either OMx or OLx is set and the IOSx bit is
set, the pin is an output regardless of the state of the corresponding DDR bit.
3. Setting an OC3M bit configures the corresponding TIMPORT pin to be output. OC3Mx makes the timer port pin an output regardless of the data
direction bit when the pin is configured for output compare (IOSx = 1). The OC3Mx bits do not change the state of the TIMDDR bits.
4. X = Don’t care
5. An output compare overrides the data direction bit of the output compare pin but does not change the state of the data direction bit. Enabling output
compare disables data register drive of the pin.
6. A successful output compare on channel 3 causes an output value determined by OC3Dx value to temporarily override the output compare pin state
of any other output compare channel.The next OC action for the specific channel will still be output to the pin. A channel 3 output compare can cause
bits in the output compare 3 data register to transfer to the timer port data register, depending on the output compare 3 mask register.