參數(shù)資料
型號(hào): MP7612AS
廠商: EXAR CORP
元件分類(lèi): DAC
英文描述: Octal 12-Bit DAC Array D/A Converter with Output Amplifier and Serial Data/Address uP Control Logic
中文描述: OCTAL, SERIAL INPUT LOADING, 30 us SETTLING TIME, 12-BIT DAC, PDSO28
封裝: 0.350 INCH, SOIC-28
文件頁(yè)數(shù): 5/20頁(yè)
文件大小: 231K
代理商: MP7612AS
MP7612
5
Rev. 3.00
25
°
C
Typ
Tmin to Tmax
Min
ELECTRICAL CHARACTERISTICS (CONT’D)
Parameter
Symbol
Min
Max
Max
Units
Test Conditions/Comments
DIGITAL INPUTS
3
Logic High
Logic Low
Input Current
Input Capacitance
1
V
IH
V
IL
2.4
V
V
μ
A
pF
0.8
+10
I
L
C
L
8
ANALOG OUTPUTS
Output Swing –V
EE
+1.4 V
CC
–1.4
Output Drive Current
Output Impedance
Output Short Circuit Current
V
mA
mA
mA
mA
mA
–5
5
R
O
I
SC
1
25
30
40
55
+FS to AGND
+FS to V
EE
–FS to AGND
–FS to V
CC
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
V
OH
V
OL
4.5
0.5
V
V
POWER SUPPLIES
V
CC
Voltage
5
V
EE
Voltage
5
DV
DD
Voltage
Positive Supply Current
Negative Supply Current
Digital Supply Current
Power Dissipation
V
CC
V
REF
+1.5
V
EE
–12.75
DV
DD
I
CC
I
EE
I
DD
PD
ISS
12
–12
12.75 V
REF
+1.5 12.75
–5
–12.75
5.5
10
20
2
420
V
V
V
mA
mA
mA
mW
–5
5.5
10
20
4.5
5
8
4.5
Bipolar zero
Bipolar zero
Bipolar zero
Bipolar zero
15
2
320
450
ANALOG GROUND CURRENT
Per Channel
1
I
AGND
±
60
μ
A
See Application Notes
DIGITAL TIMING
SPECIFICATIONS
1,4
V
IL
= 0, V
IH
= 5.0, C
L
= 20 pF
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CLK to SDO Propagation Delay
DAC Register Load Pulse Width
Preset Pulse Width
Clock Edge to Load Time
t
CH
, t
CL
35
15
15
ns
ns
ns
ns
ns
ns
ns
t
DS
t
DH
t
PD
t
LD
t
PR
40
35
50
140
t
CKLD1
t
CKLD2
t
HZ1
Note: t
LD
and t
CKLD2
cannot both
be min. since t
CKLD1
=t
CKLD2
+t
LD
0
LD Falling Edge to SDO
Tri-state Enable
LD Rising Edge to SDO
Tri-state Disable
LD Rising Edge to CLK Enable
LD Set-up Time with Respect
to CLK
50
ns
t
HZ2
50
ns
t
LDCK
t
LDSU
50
30
ns
ns
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