MP7680
8
Rev. 3.10
MUX
1
0
DAC
B1
Latch
B2
Latch
D
E
Q
D
E
Q
D
E
Q
12
4
8
8
4
12
4
8
8
4
DAC
B1
Latch
B2
Latch
D
E
Q
D
E
Q
D
E
Q
12
4
8
8
4
DAC
B1
Latch
B2
Latch
D
E
Q
D
E
Q
D
E
Q
12
4
8
8
4
DAC
B1
Latch
B2
Latch
D
E
Q
D
E
Q
D
E
Q
Latch
Address
Decoder
DA11 - DA0
LA11 - LA0
DAC LA TCHES
INPUT
LA TCHES
DB11-DB4
(MSB)
DB3-DB0
(LSB)
B1/B2
A1 (MSB)
A0 (LSB)
CS
WR1
WR2
XFER
DB11-
DB8
Enable A
Enable B
Enable C
Enable D
DB11 - DB0
DC11 - DC0
DD11 - DD0
Transfer
Disable-B1
R
FBA
I
OUT1A
I
OUT2A
R
FBB
I
OUT1B
I
OUT2B
R
FBC
I
OUT1C
I
OUT2C
R
FBD
I
OUT1D
I
OUT2D
V
REFA
V
REFB
V
REFC
V
REFD
Figure
3.
Latches
Control
Logic
THEOR Y OF OPERA TION
Digital
Interface
Figure
controls the writing of the input latches and the one that
controls the DAC latches are completely separated. It is
easy to understand how the MP7680/80A works by
understanding each basic operation.
3.
shows the internal control logic. The logic that
W riting
to Input
Latches
BykeepingB1/B2=high,a12-bitbushasdirectaccessto
the12bitsoftheinputlatches. TheconditionCS= WR1=
0 loads the values contained in the data bus DB11-DB0
into the input latch addresses by A
1
, A
0
(
Figure
Table 1.
).
4.
,