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參數資料
| 型號： | MP7680KN |
| 廠商： | EXAR CORP |
| 元件分類： | DAC |
| 英文描述： | 5 V CMOS 12-Bit Quad Double-Buffered Multiplying Digital-to-Analog Converter |
| 中文描述： | QUAD, PARALLEL, WORD INPUT LOADING, 1 us SETTLING TIME, 12-BIT DAC, PDIP40 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-40 |
| 文件頁數： | 9/12頁 |
| 文件大?。?/td> | 307K |
| 代理商： | MP7680KN |
MP7680
9
Rev. 3.10
Table 1.
DAC Selection
A0
A1
SELECTED
DAC
0
1
0
1
0
0
1
1
A
B
C
D
An 8-bit bus must use two cycles. The second cycle is
like the first one with the difference that B1/B2 = low
(
Figure
low muxes DB11-DB8 to the B2 latches (
Figure
5.
) DuringthesecondcycletheconditionB1/B2=
3.
).
Two important notes:
1)Timing diagrams show the inputs CS, A
1
, A
0
,
DB11-DB0 to be stable during the entire writing cycle.
In reality all the above signals can change (
Figure
as long as they meet the timing conditions specified in
the Electrical Characteristic Table.
2)Only16-bitbuscyclesareshowninthenextfewexam-
ples of interface timing. It is possible to generate an
8-bit interface timing by replacing a single 12-bit write
cycle (
Figure
4.
) with a double 8-bit write cycles
(
Figure
5.
)
8-bit applications should ground inputs
DB3-DB0.
4.
)
DATA
CS
WR1
B1/B2
Figure
4.
12 Bit W rite Cycle
or
Figure
5.
8-Bit Double
W rite Cycle
WR1
CS
B1/B2
DATA
High
High
to B1
to B2
to B1 & B2
A
1
, A
0
A
1
, A
0
WR2
XFER
DA11-0
or
Figure
6.
Transfer
Cycles
from Input
Latches
to DAC Latches
or
I
OUT
t
S
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