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參數(shù)資料
| 型號： | MPC106ARX66TG |
| 廠商： | MOTOROLA INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI Bridge/Memory Controller |
| 中文描述： | PCI BUS CONTROLLER, CBGA304 |
| 封裝： | 21 X 25 MM, 3.16 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-304 |
| 文件頁數(shù)： | 11/28頁 |
| 文件大?。?/td> | 158K |
| 代理商： | MPC106ARX66TG |
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MPC106 PCI Bridge/Memory Controller Hardware Specifications
11
Electrical and Thermal Characteristics
Table 8. Output AC Timing Specifications
Num
Characteristic
66 MHz
83.3 MHz
Notes
Min
Max
Min
Max
12
SYSCLK to output driven (output
enable time)
2.0
—
2.0
—
1
13a
SYSCLK to output valid for TS and
ARTRY
—
7.0
—
6.0
2, 3, 4
13b
SYSCLK to output valid for all non-PCI
signals except TS, ARTRY, RAS[0–7],
CAS[0–7], and DWE[0-2]
—
7.0
—
6.0
2, 3, 5
14a
SYSCLK to output valid (for RAS[0–7]
and CAS[0–7])
—
7.0
—
6.0
2, 3
14b
SYSCLK to output valid for PCI signals
—
11.0
—
11.0
3, 6
15a
SYSCLK to output invalid for all
non-PCI signals (output hold)
1.0
—
1.0
—
7, 10
15b
SYSCLK to output invalid for PCI
signals (output hold)
1.0
—
1.0
—
7
18
SYSCLK to ARTRY high impedance
before precharge (output hold)
—
8.0
—
8.0
1
19
SYSCLK to ARTRY precharge enable
(0.4 *
t
sysclk
) + 2.0
—
(0.4 x
t
sysclk
) + 2.0
—
8, 1
21
SYSCLK to ARTRY high impedance
after precharge
—
(1.5 *
t
sysclk
) + 8.0
—
(1.5 x
t
sysclk
) + 8.0
8, 1
Notes:
1
These values are guaranteed by design and are not tested.
2
Output specifications are measured from 1.4 V on the rising edge of the appropriate clock to the TTL level (0.8
V or 2.0 V) of the signal in question. Both input and output timings are measured at the pin (see Figure 5).
3
The maximum timing specification assumes CL = 50 pF.
4
The shared outputs TS and ARTRY require pull-up resistors to hold them negated when there is no bus master
driving them.
5
When the 106 is configured for asynchronous L2 cache SRAMs, the DWE[0–2] signals have a maximum
SYSCLK to output valid time of (0.5 x t
PROC
) + 8.0 ns (where t
PROC
is the 60x bus clock cycle time).
6
PCI 3.3 V signaling environment signals are measured from 1.65 V (Vdd ÷ 2) on the rising edge of SYSCLK to
V
OH
= 3.0 V or V
OL
= 0.3 V.
7
The minimum timing specification assumes CL = 0 pF.
8
t
sysclk
is the period of the external bus clock (SYSCLK) in nanoseconds (ns). When the unit is given as t
sysclk
the
numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in
nanoseconds) of the parameter in question.
9
PCI devices which require more than the PCI-specified hold time of T
h
= 0ns or systems where clock skew
approaches the PCI-specified allowance of 2ns may not work with the MPC106. For workarounds, see Motorola
application note
Designing PCI 2.1-Compliant MPC106 Systems
(order number AN1727/D).
相關PDF資料 |
PDF描述 |
|---|---|
| MPC106ARX83CE | PCI Bridge/Memory Controller |
| MPC106ARX83CG | PCI Bridge/Memory Controller |
| MPC106ARX83DE | PCI Bridge/Memory Controller |
| MPC106ARX83DG | PCI Bridge/Memory Controller |
| MPC106ARX83TE | PCI Bridge/Memory Controller |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MPC106ARX83CE | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:PCI Bridge/Memory Controller |
| MPC106ARX83CG | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:PCI Bridge/Memory Controller |
| MPC106ARX83DE | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:PCI Bridge/Memory Controller |
| MPC106ARX83DG | 制造商:Freescale Semiconductor 功能描述: |
| MPC106ARX83TE | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:PCI Bridge/Memory Controller |
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