參數(shù)資料
型號(hào)： MPC106ARX83CG
廠商： MOTOROLA INC
元件分類： 總線控制器
英文描述： PCI Bridge/Memory Controller
中文描述： PCI BUS CONTROLLER, CBGA304
封裝： 21 X 25 MM, 3.16 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-304
文件頁(yè)數(shù)： 24/28頁(yè)
文件大?。?/td> 158K
代理商： MPC106ARX83CG
24
MPC106 PCI Bridge/Memory Controller Hardware Specifications
System Design Information
condition may cause excessive power draw by the input receivers on the MPC106 or by other receivers in
the system. It is recommended that these signals be pulled up or restored in some manner by the system.
The 60x data bus input receivers on the MPC106 do not require pull-up resistors on the data bus signals
(DH[0–31], DL[0–31], and PAR[0–7]). However, other data bus receivers in the system may require
pull-up resistors on these signals.
In general, the 60x address and control signals are pulled up to 3.3 VDC and the PCI control signals are
pulled up to 5 VDC through weak (2–10 k
) resistors. Resistor values may need to be adjusted stronger to
reduce induced noise on specific board designs. Table 12 summarizes the pull-up/pull-down
recommendations for the MPC106.
1.8.5 Thermal Management Information
This section provides thermal management information for the C4/CBGA package. Proper thermal control
design is primarily dependent on the system-level design.
The use of C4 die on a CBGA interconnect technology offers significant reduction in both the signal delay
and the microelectronic packaging volume. Figure 14 shows the salient features of the C4/CBGA
interconnect technology. The C4 interconnection provides both the electrical and the mechanical
connections for the die to the ceramic substrate. After the C4 solder bump is reflowed, epoxy (encapsulant)
is under-filled between the die and the substrate. Under-fill material is commonly used on large high-power
die; however, this is not a requirement of the C4 technology. The package substrate is a multilayer-cofired
ceramic. The package-to-board interconnection is by an array of orthogonal 90/10 (lead/tin) solder balls on
1.27 mm pitch. During assembly of the C4/CBGA package to the board, the high-melt balls do not
collapse.
Table 12. Pull-Up/Pull-Down Recommendations
Signal Type
Signals
Pull-Up/Pull-Down
60x bus control
BR
n
TS, XATS, AACK
ARTRY
TA
Pull up to 3.3 VDC
60x bus
address/transfer
attributes
A[0–31], TT[0–4], TBST
WT, CI, GBL
Pull up to 3.3 VDC
Cache control
ADS
Pull up to 3.3 VDC
HIT, TV
Pull up to 3.3 VDC or pull-down to GND depending on
programmed polarity
PCI bus control
REQ
FRAME, IRDY
DEVSEL, TRDY, STOP
SERR, PERR
LOCK
FLSHREQ, ISA_MASTER.
Typically pull up to 5 VDC
Note: For closed systems not requiring 5V power,
these may be pulled up to 3.3 VDC.
JTAG
TRST
Pull down to GND (during normal system operation)
Factory test
LSSD_MODE
Pull up to 3.3 VDC
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