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參數(shù)資料
| 型號(hào)： | MPC2003SG60 |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 256KB and 512KB BurstRAM Secondary Cache Module for PowerPC - Based Systems |
| 中文描述： | 128K X 36 CACHE SRAM MODULE, 11 ns, DMA136 |
| 封裝： | DIMM-136 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 234K |
| 代理商： | MPC2003SG60 |
MPC2002
MPC2003
5
MOTOROLA FAST SRAM
BLOCK DIAGRAM
(See Note)
EXTERNAL
ADDRESS
16
9
9
18
16
A15 – A2
DQ0 – DQ8
INTERNAL
ADDRESS
64K x 18
MEMORY
ARRAY
ADDRESS
REGISTERS
WRITE
REGISTER
ENABLE
REGISTER
DATA–IN
REGISTERS
OUTPUT
BUFFER
BAA
K
TSP
TSC
A15 – A0
UW
LW
E
G
9
DQ9 – DQ17
9
9
9
A0
′
A1
′
A1
LOAD
D1
BINARY
COUNTER
D0
Q1
Q0
BURST LOGIC
A0
NOTE:
All registers are positive–edge triggered. The TSC or TSP signals control the duration of the burst and the start of the next
burst. When TSP is sampled low, any ongoing burst is interrupted and a read (independent of W and TSC) is performed
using the new external address. Alternatively, a TSP–initiated two cycle WRITE can be performed by asserting TSP and
a valid address on the first cycle, then negating both TSP and TSC and asserting LW and/or UW with valid data on the se-
cond cycle (see Single Write Cycle in WRITE CYCLES timing diagram).
When TSC is sampled low (and TSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on
W) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded. After
the first cycle of the burst, BAA controls subsequent burst cycles. When BAA is sampled low, the internal address is ad-
vanced prior to the operation. When BAA is sampled high, the internal address is not advanced, thus inserting a wait state
into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See
BURST
SEQUENCE GRAPH
. Write refers to either or both byte write enables (LW, UW).
BURST SEQUENCE GRAPH
(See Note)
1,0
1,1
0,0
0,1
A1
′
, A0
′
=
NOTE: The external two values for A1 and A0
provide the starting point for the burst
sequence graph. The burst logic ad-
vances A1 and A0 as shown above.
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