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參數(shù)資料
| 型號(hào)： | MPC2104 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| 中文描述： | 256KB和512KB的二級(jí)緩存模塊BurstRAM為PowerPC制備/ CH旺平臺(tái) |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 228K |
| 代理商： | MPC2104 |
MPC2104
MPC2105
MPC2106
MPC2107
7
MOTOROLA FAST SRAM
DATA RAM MCM67M518, MCM67M618 SYNCHRONOUS TRUTH TABLE
(See Notes 1, 2, and 3)
STANDBY
ADS0
CNTEN0
CWEx
CLKx
Address Used
Operation
H
L
X
X
L–H
N/A
Deselected
L
L
X
L
L–H
External Address
Write Cycle, Begin Burst
L
L
X
H
L–H
External Address
Read Cycle, Begin Burst
X
H
L
L
L–H
Next Address
Write Cycle, Continue Burst
X
H
L
H
L–H
Next Address
Read Cycle, Continue Burst
X
H
H
L
L–H
Current Address
Write Cycle, Suspend Burst
X
H
H
H
L–H
Current Address
Read Cycle, Suspend Burst
NOTES:
1. X means Don’t Care.
2. All inputs except COE must meet set–up and hold times for the low–to–high transition of clock (CLK0 – CLK4).
3. Wait states are inserted by suspending burst.
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2)
Operation
COE
I/O Status
Read
L
Data Out (DQ0 – DQ8)
Read
H
High–Z
Write
X
High–Z — Data In
Deselected
X
High–Z
NOTES:
1. X means Don’t Care.
2. For a write operation following a read operation, COE must be high before the input
data required set–up time and held high through the input data hold time.
DATA RAM MCM6206 ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2)
STANDBY
COE0, COE1
CWE0 – CWE7
Operation
I/O Status
H
X
X
Deselected
High–Z
L
H
Output Disabled
High–Z
L
L
H
Read
Data Out
L
X
L
Write
High–Z
NOTES:
1. X means Don’t Care.
2. For a write operation following a read operation, COE0, and COE1 must be high before the input data required set–up time, and held high
through the input data hold time.
ABSOLUTE MAXIMUM RATINGS
(Voltages Referenced to VSS = 0 V)
Rating
Symbol
Value
Unit
Power Supply Voltage
VCC
– 0.5 to + 7.0
V
Voltage Relative to VSS
Vin, Vout
– 0.5 to VCC + 0.5
V
Output Current (per I/O)
Data RAM
Tag
Iout
±
30
±
20
mA
Power Dissipation
PD
8.1
W
Temperature Under Bias
Tbias
– 10 to + 85
°
C
Operating Temperature
TA
0 to +70
°
C
Storage Temperature
Tstg
– 55 to + 125
°
C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will
ensure the output devices are in High–Z at
power up.
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| MPC2104P | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:256KB/512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2104PDG66 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:256KB/512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2104SG66 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2105A | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2105ASG66 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
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