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參數(shù)資料
| 型號(hào)： | MPC2104P |
| 廠商： | Motorola, Inc. |
| 英文描述： | 256KB/512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| 中文描述： | 256KB/512KB BurstRAM二級(jí)緩存模塊為PowerPC制備/ CH旺平臺(tái) |
| 文件頁(yè)數(shù)： | 8/16頁(yè) |
| 文件大?。?/td> | 158K |
| 代理商： | MPC2104P |
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MPC2104P
MPC2105P
8
MOTOROLA FAST SRAM
DATA RAMs AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
5%, VDD = 3.3 V + 10%, – 5%, TA = 0 to + 70
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . .
0 to 3.0 V
3 ns
Output Timing Reference Level
Output Load
. . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
See Figure 1a Unless Otherwise Noted
SYNCHRONOUS DATA RAMs READ/WRITE CYCLE TIMING
(See Notes 1 and 2)
Parameter
Symbol
b l
MPC2104P/5P
U i
Unit
Notes
Min
Max
Cycle Time
tKHKH
tKHQV
tGLQV
tKHQX1
tKHQX2
tGLQX
tGHQZ
tKHQZ
tKHKL
tKLKH
tAVKH
tSVKH
tDVKH
tWVKH
tBAVVKH
tEVKH
15
—
ns
Clock Access Time
—
8
ns
3
Output Enable to Output Valid
—
6
ns
Clock High to Output Active
0
—
ns
Clock High to Output Change
2
—
ns
Output Enable to Output Active
0
—
ns
Output Disable to Q High–Z
—
8
ns
Clock High to Q High–Z
2
8
ns
Clock High Pulse Width
5
—
ns
Clock Low Pulse Width
5
—
ns
Setup Times:
Address
Address Status
Data In
Write
Address Advance
Chip Enable
2.5
—
ns
4
Hold Times:
Address
Address Status
Data In
Write
Address Advance
Chip Enable
tKHAX
tKHTSX
tKHDX
tKHWX
tKHBAX
tKHEX
0.5
—
ns
4
NOTES:
1. All read and write cycle timings are referenced from CLK or CG0.
2. CG is a don’t care when CWEx is sampled low.
3. Maximum access times are guaranteed for all possible PowerPC external bus cycles.
4. This is a synchronous device. All addresses must meet the specified setup and hold times for
ALL
rising edges of CLK whenever ADS0
is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for
ALL
rising edges of
CLK when the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when ADS0 is low) to remain enabled.
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