- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371134 > MPC2105A (Motorola, Inc.) 512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms PDF資料下載
參數(shù)資料
| 型號(hào)： | MPC2105A |
| 廠商： | Motorola, Inc. |
| 英文描述： | 512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| 中文描述： | 512KB和1MB的二級緩存模塊BurstRAM為PowerPC制備/ CH旺平臺(tái) |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 245K |
| 代理商： | MPC2105A |
MPC2105A
MPC2106A
MPC2105B
MPC2106B
8
MOTOROLA FAST SRAM
DATA RAMs AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
5%, VDD = 3.3 V
±
10% TA = 0 to + 70
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . .
0 to 3.0 V
3 ns
Output Timing Reference Level
Output Load
. . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
See Figure 1a Unless Otherwise Noted
SYNCHRONOUS DATA RAMs READ/WRITE CYCLE TIMING
(See Notes 1, 2, and 3)
MPC2105A/B
MPC2106A/B
Parameter
Symbol
Min
Max
Unit
Notes
Cycle Time
tKHKH
tKHQV
tGLQV
tKHQX1
tKHQX2
tGLQX
tGHQZ
tKHQZ
tKHKL
tKLKH
tAVKH
tSVKH
tDVKH
tWVKH
tBAVVKH
tEVKH
15
—
ns
Clock Access Time
—
9
ns
4
Output Enable to Output Valid
—
5
ns
Clock High to Output Active
6
—
ns
Clock High to Output Change
3
—
ns
Output Enable to Output Active
0
—
ns
Output Disable to Q High–Z
2
6
ns
Clock High to Q High–Z
—
6
ns
Clock High Pulse Width
5
—
ns
Clock Low Pulse Width
5
—
ns
Setup Time
Address
7.5
—
ns
5, 6
Setup Times:
Address Status
Data In
Write
Address Advance
Chip Enable
2.5
—
ns
5
Hold Times:
Address
Address Status
Data In
Write
Address Advance
Chip Enable
tKHAX
tKHTSX
tKHDX
tKHWX
tKHBAX
tKHEX
0.5
—
ns
5
NOTES:
1. In setup and hold times, W (write) refers to either one or both byte write enables LW and UW.
2. All read and write cycle timings are referenced from CLK or CG.
3. CG is a don’t care when UW or LW is sampled low.
4. Maximum access times are guaranteed for all possible PowerPC external bus cycles.
5. This is a synchronous device. All addresses must meet the specified setup and hold times for
ALL
rising edges of CLK whenever TSP or
TSC is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for
ALL
rising edges of
CLK when the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when TSP or TSC is low) to remain
enabled.
6. 5 ns of setup delay is incurred in address buffers.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC2106CDG66 | 512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2106BSG66 | 512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2107SG15 | 256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2105PDG66 | 256KB/512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2104 | 256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC2105ASG66 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2105BSG66 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2105C | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2105CDG66 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2105PDG66 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:256KB/512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。