參數(shù)資料
型號: MPC5200CVR400B
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 400 MHz, MICROPROCESSOR, PBGA272
封裝: 27 X 27 MM, 1.27 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-272
文件頁數(shù): 13/78頁
文件大?。?/td> 1100K
代理商: MPC5200CVR400B
MPC5200B Data Sheet, Rev. 1
Electrical and Thermal Characteristics
Freescale Semiconductor
20
3.3.5
SDRAM
3.3.5.1
Memory Interface Timing-Standard SDRAM Read Command
Figure 5. Timing Diagram—Standard SDRAM Memory Read Timing
3.3.5.2
Memory Interface Timing-Standard SDRAM Write Command
In Standard SDRAM, all signals are activated on the MEM_CLK from the Memory Controller and
captured on the MEM_CLK clock at the memory device.
Table 18. Standard SDRAM Memory Read Timing
Sym
Description
Min
Max
Units
SpecID
tmem_clk MEM_CLK period
7.5
ns
A5.1
tvalid
Control Signals, Address and MBA Valid after
rising edge of MEM_CLK
—tmem_clk*0.5+0.4
ns
A5.2
thold
Control Signals, Address and MBA Hold after
rising edge of MEM_CLK
tmem_clk*0.5
ns
A5.3
DMvalid
DQM valid after rising edge of MEM_CLK
tmem_clk*0.25+0.4
ns
A5.4
DMhold
DQM hold after rising edge of MEM_CLK
tmem_clk*0.25-0.7
ns
A5.5
datasetup MDQ setup to rising edge of MEM_CLK
0.3
ns
A5.6
datahold MDQ hold after rising edge of MEM_CLK
0.2
ns
A5.7
MEM_CLK
Control Signals
MDQ (Data)
MA (Address)
NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN
Active
NOP
READ
NOP
thold
Row
Column
MBA (Bank Selects)
tvalid
thold
tvalid
thold
tvalid
DQM (Data Mask)
DMvalid
DMhold
NOP
datahold
datasetup
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