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參數(shù)資料
| 型號： | MPC5200VR400BR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 1/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 400MHZ 272-PBGA |
| 標準包裝： | 500 |
| 系列： | MPC52xx |
| 核心處理器： | e300 |
| 芯體尺寸： | 32-位 |
| 速度： | 400MHz |
| 連通性： | CAN，EBI/EMI，以太網(wǎng)，I²C，IrDA，J1850，SPI，UART/USART，USB |
| 外圍設(shè)備： | AC'97，DMA，I²S，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 56 |
| 程序存儲器類型： | 外部程序存儲器 |
| RAM 容量： | 16K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.42 V ~ 1.58 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 272-BBGA |
| 包裝： | 帶卷 (TR) |
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Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MPC5200BDS
Rev. 4, 02/2010
Freescale Semiconductor, Inc., 2008, 2010. All rights reserved.
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
TEPBGA–272
27 mm x 27 mm
Key features are shown below.
MPC603e series e300 core
– Superscalar architecture
– 760 MIPS at 400 MHz (–40 oC to +85 oC)
– 16 KB Instruction cache, 16 KB Data cache
– Double precision FPU
– Instruction and Data MMU
– Standard and Critical interrupt capability
SDRAM / DDR Memory Interface
– Up to 133 MHz operation
– SDRAM and DDR SDRAM support
– 256 MB addressing range per CS, two CS available
– 32-bit data bus
– Built-in initialization and refresh
Flexible multi-function External Bus Interface
– Supports interfacing to ROM/Flash/SRAM memories or
other memory mapped devices
– 8 programmable Chip Selects
– Non-multiplexed data access using 8-/16-/32-bit databus
with up to 26-bit address
– Short or Long Burst capable
– Multiplexed data access using 8-/16-/32-bit databus
with up to 25-bit address
Peripheral Component Interconnect (PCI) Controller
– Version 2.2 PCI compatibility
– PCI initiator and target operation
– 32-bit PCI Address/Data bus
– 33 and 66 MHz operation
– PCI arbitration function
ATA Controller
– Version 4 ATA compatible external interface—IDE Disk
Drive connectivity
BestComm DMA subsystem
– Intelligent virtual DMA Controller
– Dedicated DMA channels to control peripheral
reception and transmission
– Local memory (SRAM 16 KB)
6 Programmable Serial Controllers (PSC)
– UART or RS232 interface
– CODEC interface for Soft Modem, Master/Slave
CODEC Mode, I2S and AC97
– Full duplex SPI mode
– IrDA mode from 2400 bps to 4 Mbps
Fast Ethernet Controller (FEC)
– Supports 100Mbps IEEE 802.3 MII, 10 Mbps IEEE
802.3 MII, 10 Mbps 7-wire interface
Universal Serial Bus Controller (USB)
– USB Revision 1.1 Host
– Open Host Controller Interface (OHCI)
– Integrated USB Hub, with two ports.
Two Inter-Integrated Circuit Interfaces (I2C)
Serial Peripheral Interface (SPI)
Dual CAN 2.0 A/B Controller (MSCAN)
– Implementation of version 2.0A/B CAN protocol
– Standard and extended data frames
J1850 Byte Data Link Controller (BDLC)
J1850 Class B data communication network interface
compatible and ISO compatible for low speed (<125 kbps)
serial data communications in automotive applications.
Supports 4X mode, 41.6 kbps
In-frame response (IFR) types 0, 1, 2, and 3 supported
Systems level features
– Interrupt Controller supports four external interrupt
request lines and 47 internal interrupt sources
– GPIO/Timer functions
Up to 56 total GPIO pins that support a variety of
interrupt/WakeUp capabilities.
Eight GPIO pins with timer capability supporting input
capture, output compare, and pulse width modulation
(PWM) functions
– Real-time Clock with one-second resolution
– Systems Protection (watch dog timer, bus monitor)
– Individual control of functional block clock sources
– Power management: Nap, Doze, Sleep, Deep Sleep
modes
– Support of WakeUp from low power modes by different
sources (GPIO, RTC, CAN)
Test/Debug features
– JTAG (IEEE 1149.1 test access port)
– Common On-chip Processor (COP) debug port
On-board PLL and clock generation
MPC5200B Data Sheet
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