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參數(shù)資料
| 型號(hào)： | MPC536CZP40 |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 15/16頁(yè) |
| 文件大小： | 0K |
| 描述： | IC MCU 1M FLASH 40MHZ 388-BGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | MPC5xx |
| 核心處理器： | PowerPC |
| 芯體尺寸： | 32-位 |
| 速度： | 40MHz |
| 連通性： | CAN，EBI/EMI，SCI，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 56 |
| 程序存儲(chǔ)器容量： | 1MB（1M x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 36K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.5 V ~ 2.7 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 388-BBGA |
| 包裝： | 托盤(pán) |
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8
MPC535/MPC536 Product Brief
MOTOROLA
Additional MPC535 Differences
2.1
Additional MPC535 Differences
The following are additional differences between the MPC555 and the MPC535.
SPI (MISO, MOSI, and SCK) pin drive.
— MPC535 provides 21-ns rise/fall with 200-pf load using CMOS (20%/70%) levels
GPIO on MODCK1 pin outputs only 2.6 V
— MODCK1 pin is in keep-alive power section with no 5-V rail available
— 5.0-V compatibility modes
– Input is 5-V friendly
– 2.6-V output has less slew rate control
– 2.6-V: VOH = 2.3 V
Power supplies for external bus pins
— QVDDL is quiet supply to hold non-switching outputs quiet even when noisy supply
(NVDDL) sags
— QVDDL supplies pre-drive and other pad logic
— NVDDL only supplies final PMOS driver stage
— QVDDL and NVDDL shorted on customer board after filtering
Pull-up and pull-down changes during PORESET and HRESET
— All 2.6-V/5-V pads (external bus: address/data/control) pull down at reset
— All 5-V pads pull up at reset
— Additional control granularity in the PDMCR register
No pull-ups on QSMCM SCI receive pads
A_RXD1_QGPI1, A_RXD2_QGPI2 pins do not have weak pull-up during reset or any other time
CLKOUT has 3 drive strength options
— Better matches drive to requirements to reduce EMI
— 25, 50, 100 pf instead of 45 and 90 pf
Change reset value of ENGCLK to maximum divide (crystal/128)
— For a 4-MHz crystal, this is 31.25 KHz
– ENGCLK is selectable between 2.6 V and 5 V
A daisy chain between UC3F modules allows either module to provide the reset configuration
word (RCW)
Censorship operation
— A RCW bit controls whether or not the entire UC3F can be erased while censorship is violated
BBC SPRs (PPC regs) access in two clocks instead of one clock
CALRAM internal protection block size is 8 Kbytes
— Instead of 4 Kbytes on MPC555 LRAM
CALRAM causes machine check exception instead of data storage interrupt (DSI) exception in
certain cases
— For non-overlay CPU core accesses, a DSI exception is taken
— For overlay accesses and any non-core access (slave mode), a machine check exception is
taken
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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