參數(shù)資料
型號： MPC5533MZQ66
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： FLASH, 66 MHz, MICROCONTROLLER, PBGA324
封裝： 23 X 23 MM, 1 MM PITCH, MO-034AAJ-1, PLASTIC, TEPBGA-324
文件頁數(shù)： 29/50頁
文件大?。?/td> 1080K
代理商： MPC5533MZQ66
Electrical Characteristics
MPC5533 Microcontroller Data Sheet, Rev. 0.0
Freescale Semiconductor
35
3.13.5
External Interrupt Timing (IRQ Signals)
7 5
Input signal valid to
CLKOUT positive edge
(setup time)
External bus interface
ADDR[8:31]
DATA[0:15]
RD_WR
TS
TA
tCIS
10.0
—10.0—
10.0
—ns
8 5
CLKOUT positive edge to
input signal invalid (hold
time)
External bus interface
ADDR[8:31]
DATA[0:15]
RD_WR
TS
TA
tCIH
1.0
—1.0
—
1.0
—ns
1 EBI timing specified at V
DDE = 1.6–3.6 V (unless stated otherwise), TA = TL to TH, and CL = 30 pF with DSC = 0b10.
2 The external bus is limited to half the speed of the internal bus.
3 Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM).
42 MHz parts allow for 40 MHz system clock + 2% FM; 68 MHz parts allow for a 66 MHz system clock + 2% FM, and
82 MHz parts allow for 80 MHz system clock + 2% FM.
4 Refer to fast pad timing in Table 17 and Table 18 (different values for 1.8 V and 3.3 V).
5 Available on the 324 package only; not available on the 208 package.
6 EBTS = 0 timings are tested and valid at V
DDE = 2.25–3.6 V only; EBTS = 1 timings are tested and valid at VDDE = 1.6–3.6 V.
Table 23. External Interrupt Timing 1
1 IRQ timing specified at: V
DDEH = 3.0–5.25 V and TA = TL to TH.
Spec
Characteristic
Symbol
Min.
Max.
Unit
1
IRQ pulse-width low
tIPWL
3—
tCYC
2
IRQ pulse-width high
TIPWH
3—
tCYC
3
IRQ edge-to-edge time 2
2 Applies when IRQ signals are configured for rising-edge or falling-edge events, but not both.
tICYC
6—
tCYC
Table 22. External Bus Operation Timing1, 2 (continued)
Spec
Characteristic
and
Description
Symbol
External Bus Frequency 3
Unit
Notes
20 MHz
33 MHz
40 MHz
Min.
Max
Min.
Max
Min.
Max
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