參數(shù)資料
型號： MPC5534
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： Microcontroller
中文描述： 微控制器
文件頁數(shù)： 20/50頁
文件大?。?/td> 1148K
代理商： MPC5534
MPC5534 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
Electrical Characteristics
Freescale Semiconductor
20
3.10
eQADC Electrical Characteristics
20
Frequency Modulation Range Limit
14
(f
sys
Max must not be exceeded)
ICO Frequency.
f
ico
=[f
ref
*(MFD+4)]/(PREDIV+1)
15
Predivider Output Frequency (to PLL)
C
mod
0.8
2.4
%f
sys
21
f
ico
48
80
16
MHz
22
f
PREDIV
4
f
MAX
MHz
1
All internal registers retain data at 0 Hz.
2
Up to the maximum frequency rating of the device (see
Table 1
).
3
“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode.
4
Self clocked mode (SCM) frequency is the frequency that the PLL operates at when the reference frequency falls below f
LOR
.
This frequency is measured on the CLKOUT pin with the divider set to divide-by-2 of the system clock. NOTE: In SCM, the
MFD and PREDIV have no effect and the RFD is bypassed.
5
This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case,
V
extal
– V
xtal
>= 400mV criteria has to be met for oscillator’s comparator to produce output clock.
6
This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case,
V
xtal
– V
extal
>= 400mV criteria has to be met for oscillator’s comparator to produce output clock.
7
I
xtal
is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.
8
C
PCB_EXTAL
and C
PCB_XTAL
are the measured PCB stray capacitances on EXTAL and XTAL, respectively
9
This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR). From power up with crystal oscillator reference, the lock time will also include the crystal
startup time.
10
PLL is operating in 1:1 PLL mode.
11
VDDE = 3.0 to 3.6V
12
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
sys
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via V
DDSYN
and V
SSSYN
and variation in crystal oscillator frequency increase the jitter percentage
for a given interval. CLKOUT divider set to divide-by-2.
13
Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of jitter + Cmod.
14
Modulation depth selected must not result in f
sys
value greater than the f
sys
maximum specified value.
15
f
sys
= f
ico
/ (2
RFD
)
16
Note that the ICO frequency may be higher than the maximum allowable system frequency, in that case, the FMPLL
Synthesizer Control Register Reduced Frequency Divider (FMPLL_SYNCR[RFD]) must be set to divide by 2 (RFD=0b001). In
other words, for a 40 MHz maximum device (system frequency), the FMPLL should be programmed to generate 80 MHz at the
ICO output and then divided by 2 by the RFD to provide the 40 MHz system clock.
Table 13. eQADC Conversion Specifications (Operating)
Num
Characteristic
Symbol
Min
Max
Unit
1
ADC Clock (ADCLK) Frequency
1
F
ADCLK
CC
1
12
MHz
2
Conversion Cycles
Differential
Single Ended
Stop Mode Recovery Time
2
13+2 (or 15)
14+2 (or 16)
13+128 (or 141)
14+128 (or 142)
ADCLK
cycles
3
T
SR
10
—
μ
s
Table 12. HiP7 FMPLL Electrical Specifications (continued)
(V
DDSYN
= 3.0V to 3.6 V, V
SS
= V
SSSYN
= 0 V, T
A
= T
L
to T
H
)
Num
Characteristic
Symbol
Min.
Value
Max.
Value
Unit
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