參數(shù)資料
型號(hào)： MPC5553MVZ132
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 59/68頁(yè)
文件大小： 0K
描述： MCU 1.5MB FLASH 132MHZ 324-PBGA
標(biāo)準(zhǔn)包裝： 60
系列： MPC55xx Qorivva
核心處理器： e200z6
芯體尺寸： 32-位
速度： 132MHz
連通性： CAN，EBI/EMI，以太網(wǎng)，SCI，SPI
外圍設(shè)備： DMA，POR，PWM，WDT
輸入/輸出數(shù)： 220
程序存儲(chǔ)器容量： 1.5MB（1.5M x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 64K x 8
電壓 - 電源 (Vcc/Vdd)： 1.35 V ~ 1.65 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 40x12b
振蕩器型： 外部
工作溫度： -40°C ~ 125°C
封裝/外殼： 324-BBGA
包裝： 托盤(pán)
MPC5553 Microcontroller Data Sheet, Rev. 4
Revision History for the MPC5553 Data Sheet
Freescale Semiconductor
62
The following table describes the changes made to information in tables and figures, and is presented in
sequential page number order.
Added the sentence directly preceding Table 1: ‘Unless noted in this data sheet, all specifications apply
from TL to TH.’
First paragraph, text changed from “based on the PowerPC Book E architecture” to “built on the Power
Architecture embedded technology.”
Second paragraph: Changed terminology from PowerPC Book E architecture to Power Architecture terminology.
3.7.1, 3.7.2 and 3.7.3: Reordered sections resulting in the following order and section renumbering:
From:
‘To avoid accidentally selecting the bypass clock because PLLCFG[0:1] and RSTCFG are not treated as ones
(1s) when POR negates, VDD33 must not lag VDDSYN and the RESET pin power (VDDEH6) when powering the
device by more than the VDD33 lag specification in Table 6 (VRC and POR Electrical Specifications). VDD33
individually can lag either VDDSYN or the RESET power pin (VDDEH6) by more than the VDD33 lag specification.
VDD33 can lag one of the VDDSYN or VDDEH6 supplies, but cannot lag both by more than the VDD33 lag
specification. This VDD33 lag specification only applies during power up. VDD33 has no lead or lag requirements
when powering down.’
To:
‘When powering the device, VDD33 must not lag VDDSYN and the RESET power pin (VDDEH6) by more than the
VDD33 lag specification listed in Table 6 (VRC and POR Electrical Specifications). This avoids accidentally
selecting the bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered
and therefore cannot read the default state when POR negates. VDD33 can lag VDDSYN or the RESET power pin
(VDDEH6), but cannot lag both by more than the VDD33 lag specification. This VDD33 lag specification only applies
during power up. VDD33 has no lead or lag requirements when powering down.’
Added the following text directly before this section and after Table 8 (Pin Status for Medium and Slow Pads During
the Power Sequence) Pin Status for Medium / Slow Pads During the Power-on Sequence:
and Slow Pads During the Power Sequence) do not include the effect of the weak pull devices on the output pins
during power up.
Before exiting the internal POR state, the voltage on the pins goes to high-impedance until POR negates. When
the internal POR negates, the functional state of the signal during reset applies and the weak pull devices (up or
down) are enabled as defined in the device Reference Manual. If VDD is too low to correctly propagate the logic
signals, the weak-pull devices can pull the signals to VDDE and VDDEH.
To avoid this condition, minimize the ramp time of the VDD supply to a time period less than the time required to
enable the external circuitry connected to the device outputs.’
Table 32. Global and Text Changes Between Rev. 2.0 and 3.0 (continued)
Location
Description of Change
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