參數(shù)資料
型號(hào)： MPC555PB
廠商： Motorola, Inc.
英文描述： CABLE ASSEMBLY; ; NMO Antenna Mount to BNC Male, RG58C/U, 5 feet
中文描述： 本文件提供了對(duì)MPC555的微控制器的概述，包括1塊示意圖主要模塊化組件和部門，即待
文件頁數(shù)： 3/12頁
文件大小： 171K
代理商： MPC555PB
MOTOROLA
MPC555 Product Brief
3
Key Features
1.2.2
U-Bus System Interface Unit (USIU)
Clock synthesizer
Power management
Reset controller
MPC555 decrementer and time base
Real-time clock register
Periodic interrupt timer
Hardware bus monitor and software watchdog timer
Interrupt controller that supports up to eight external and eight internal interrupts
IEEE 1149.1 JTAG test access port
External bus interface
— 24 address pins, 32 data pins
— Supports multiple master designs
— Four-beat transfer bursts, two-clock minimum bus transactions
— Supports 5V inputs, provides 3.3-V outputs
1.2.3
Flexible Memory Protection Unit
Four instruction regions and four data regions
4-Kbyte to 16-Mbyte region size support
Default attributes available in one global entry
Attribute support for speculative accesses
1.2.4
448-Kbyte Flash EEPROM Memory
One 256-Kbyte and one 192-Kbyte module
Page read mode
Block (32-Kbyte) erasable
External 4.75-V to 5.25-V program and erase power supply
1.2.5
26-Kbytes of Static RAM
One 16-Kbyte and one 10-Kbyte module
Fast (one-clock) access
Keep-alive power
Soft defect detection (SDD)
1.2.6
General-Purpose I/O Support
Address (24) and data (32) pins can be used for general-purpose I/O in single-chip mode
Nine general-purpose I/O pins in MIOS1 unit
Many peripheral pins can be used for general-purpose I/O when not used for primary function
5-V tolerant inputs/outputs
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