Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MPC5604BC
Rev. 9, 06/2011
Freescale Semiconductor, Inc., 2009-2011. All rights reserved.
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
MPC5604B/C
TBD
MAPBGA–225
15 mm x 15 mm
QFN12
##_mm_x_##mm
SOT-343R
##_mm_x_##mm
PKG-TBD
## mm x ## mm
208 MAPBGA
(17 x 17 x 1.7 mm)
144 LQFP
(20 x 20 x 1.4 mm)
100 LQFP
(14 x 14 x 1.4 mm)
64 LQFP
(10 x 10 x 1.4 mm)
Features
Single issue, 32-bit CPU core complex (e200z0)
— Compliant with the Power Architecture
embedded category
— Includes an instruction set enhancement
allowing variable length encoding (VLE) for
code size footprint reduction. With the optional
encoding of mixed 16-bit and 32-bit
instructions, it is possible to achieve significant
code size footprint reduction.
Up to 512 KB on-chip code flash supported with the
flash controller
64 (4 × 16) KB on-chip data flash memory with ECC
Up to 48 KB on-chip SRAM
Memory protection unit (MPU) with 8 region
descriptors and 32-byte region granularity
Interrupt controller (INTC) with 148 interrupt
vectors, including 16 external interrupt sources and
18 external interrupt/wakeup sources
Frequency modulated phase-locked loop (FMPLL)
Crossbar switch architecture for concurrent access to
peripherals, flash memory, or RAM from multiple
bus masters
Boot assist module (BAM) supports internal flash
programming via a serial link (CAN or SCI)
Timer supports input/output channels providing a
range of 16-bit input capture, output compare, and
pulse width modulation functions (eMIOS-lite)
10-bit analog-to-digital converter (ADC)
3 serial peripheral interface (DSPI) modules
Up to 4 serial communication interface (LINFlex)
modules
MPC5604B/C
Microcontroller Data Sheet
3.7
Nexus 2+ pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29