Queued Serial Multi-Channel Module
MPC561/MPC563 Reference Manual, Rev. 1.2
15-8
Freescale Semiconductor
Figure 15-3. Interrupt Hardware Block Diagram
15.4.5
QSPI Interrupt Generation
15.4.6
QSMCM Configuration Register (QSMCMMCR)
The QSMCMMCR contains parameters for interfacing to the CPU and the intermodule bus. This register
can be modified only when the CPU is in supervisor mode.
MSB
0
1
23456
7
8
9
10
11
12
13
14
LSB
15
Field STOP
FRZ1
—
SUPV
—
SRESET
0
00_0000
1
000_0000
Addr
0x30 5000
Figure 15-4. QSMCM Configuration Register (QSMCMMCR)
IRQ[7:0]
Interrupt
Level
Encoder
ILBS[0:1]
SCI1 and 2 Int
QSPI[4:0] Int
Lev Reg. [4:0]
2
Lev Reg. [4:0]
5
SCI_1 Interrupt
SCI_2 Interrupt
QSPI Interrupt
8
Interrupt
Level
Decoder
8
