
A-20
MPC565/MPC566 Reference Manual
MOTOROLA
Index of Memory Map Tables
0x30 5540 –
0x30 557F
S/U
RECRAM_B
Receive Data RAM
16
S
0x30 5580 –
0x30 55BF
S/U
TRAN.RAM_B
Transmit Data RAM
16
S
0x30 55C0 –
0x30 55DF
S/U
COMD.RAM_B
Command RAM
16
S
1 Bits 0–3 writeable only in test mode, otherwise read only.
2 Bits 3–11 writeable only in test mode, otherwise read only.
3 Bits 0–3 writeable only in test mode, otherwise read only.
4 Bits 3–11 writeable only in test mode, otherwise read only.
Table A-13. Time Processor Unit 3 C (TPU3_C)
Address
Access
Symbol
Register
Size
Reset
TPU_C
0x30 5C001
S 1
TPUMCR_C
TPU3_C Module Configuration Register
16 only
S, M
0x30 5C02
T
TCR_C
TPU3_C Test Configuration Register
16
S, M
0x30 5C04
S
DSCR_C
TPU3_C Development Support Control
Register
16 2
S, M
0x30 5C06
S
DSSR_C
TPU3_C Development Support Status
Register
162
S, M
0x30 5C08
S
TICR_C
TPU3_C Interrupt Configuration Register
162
S, M
0x30 5C0A
S
CIER_C
TPU3_C Channel Interrupt Enable Register
162
S, M
0x30 5C0C
S
CFSR0_C
TPU3_C Channel Function Selection
Register 0
162
S, M
0x30 5C0E
S
CFSR1_C
TPU3_C Channel Function Selection
Register 1
162
S, M
0x30 5C10
S
CFSR2_C
TPU3_C Channel Function Selection
Register 2
162
S, M
0x30 5C12
S
CFSR3_C
TPU_C Channel Function Selection
Register 3
162
S, M
0x30 5C14
S/U 3
HSQR0_C
TPU_C Host Sequence Register 0
162
S, M
0x30 5C16
S/U3
HSQR1_C
TPU_C Host Sequence Register 1
162
S, M
0x30 5C18
S/U3
HSRR0_C
TPU_C Host Service Request Register 0
162
S, M
0x30 5C1A
S/U3
HSRR1_C
TPU_C Host Service Request Register 1
162
S, M
0x30 5CC
S
CPR0_C
TPU_C Channel Priority Register 0
162
S, M
0x30 5C1E
S
CPR1_C
TPU_C Channel Priority Register 1
162
S, M
0x30 5C20
S
CISR_C
TPU_C Channel Interrupt Status Register
16
S, M
Table A-12. QSMCM A and B (Queued Serial Multi-Channel Module) (continued)
Address
Access
Symbol
Register
Size
Reset