
MOTOROLA
Chapter 10. Memory Controller
10-23
Chip-Select Timing
Figure 10-18. Consecutive Accesses
(Read After Read From Same Bank, EHTR = 1)
10.3.5 Summary of GPCM Timing Options
Table 10-2 summarizes the different combinations of timing options.
Table 10-2. Programming Rules for Timing Strobes
TRLX
Access
Type
ACS
CSNT
Address
to CS
Asserted
CS
Negated to
Add/Data
Invalid
Address to
WE/BE or
OE
Asserted
WE/BE
Negated to
Add/Data
Invalid
OE
Negated to
Add/Data
Invalid
Total
Number of
Cycles
0
read
00
X
0
1/4 * clock
3/4 * clock
X
1/4 * clock
2 + SCY
0
read
10
X
1/4 * clock
3/4 * clock
X
1/4 * clock
2 + SCY
0
read
11
X
1/2 * clock
1/4 * clock
3/4 * clock
X
1/4 * clock
2 + SCY
0
write
00
0
1/4 * clock
3/4 * clock
1/4 * clock
X
2 + SCY
0
write
10
0
1/4 * clock
3/4 * clock
1/4 * clock
X
2 + SCY
0
write
11
0
1/2 * clock
1/4 * clock
3/4 * clock
1/4 * clock
X
2 + SCY
Clock
Address
TS
TA
CSx
CSy
RD/WR
Data
OE
Tdt