2-60
MPC565/MPC566 Reference Manual
MOTOROLA
Package Description
2.8.2
Bumped Die
The MPC565/MPC566 is available as known good die (KGD) in a bumped die
configuration. The bump pitch is 7 mils and the bump configuration is shown in
Figure 2-9.Figure 2-15 show the pins in a larger diagram in black and white.
Figure 2-9. MPC565/MPC566 Redistributed Bump Map
7mil tracepitch
VSS
VSSRTC
EXTAL32
XTAL32
VDDRTC
VDDSRAM1
VDDSRAM2
VDDSRAM3
B_CNTX0
C_T2CLK
C_TPUCH15
C_TPUCH14
C_TPUCH13
C_TPUCH12
C_TPUCH11
C_TPUCH10
C_TPUCH9
C_TPUCH8
C_TPUCH7
C_TPUCH6
C_TPUCH5
C_TPUCH4
C_TPUCH3
C_TPUCH2
C_TPUCH1
C_TPUCH0
MCKI
MDI_0
TCK_DSCK
MDI_1
MSEI_B
TDI_DSDI
EVTI_B
RSTI_B
TMS
MDO_4_MPIO32B10
MDO_5_MPIO32B9
MDO_6_MPIO32B8
MDO_7_MPIO32B7
NVDDL
VSS
JCOMP
MCKO
MDO_0
MDO_1
TDO_DSDO
MDO_2
MDO_3
MSEO_B
NVDDL
VSS
IWP0_VFLS0
IWP1_VFLS1
ADDR_SGPIOA16
ADDR_SGPIOA17
SGPIOC6_FRX_PTR_B
ADDR_SGPIOA8
ADDR_SGPIOA18
NVDDL
VSS
ADDR_SGPIOA19
ADDR_SGPIOA9
ADDR_SGPIOA10
ADDR_SGPIOA20
ADDR_SGPIOA21
ADDR_SGPIOA11
ADDR_SGPIOA12
ADDR_SGPIOA22
NVDDL
VSS
ADDR_SGPIOA23
ADDR_SGPIOA13
ADDR_SGPIOA24
ADDR_SGPIOA25
ADDR_SGPIOA14
ADDR_SGPIOA15
ADDR_SGPIOA30
ADDR_SGPIOA26
NVDDL
VSS
ADDR_SGPIOA27
ADDR_SGPIOA31
ADDR_SGPIOA28
ADDR_SGPIOA29
QVDDL
VSS
QVDDL
VSS
QVDDL
VDD
VDDH
DATA_
SGP
IOA0
DAT
A_
S
G
P
IOA2
9
DAT
A_
S
G
P
IOA1
DATA_
SGP
IOA2
NVDDL
VS
S
DAT
A_
S
G
P
IOA3
DAT
A_
S
G
P
IOA2
7
DATA_
SGP
IOA4
DAT
A_
SGPI
OA2
8
DAT
A_
SGPI
OA3
1
DAT
A_
S
G
P
IOA5
NVDDL
VS
S
DAT
A_
S
G
P
IOA6
DAT
A_
SGPI
OA3
0
DAT
A_
SGPI
OA7
DAT
A_
SGPI
OA2
5
DAT
A_
SGPI
OA8
DAT
A_
SGPI
OA2
4
DAT
A_
SGPI
OA9
DAT
A_
SGPI
OA1
0
NVDDL
VSS
DAT
A_
SGPI
OA2
6
DAT
A_
SGPI
OA2
2
DAT
A_
SGPI
OA1
1
DAT
A_
SGPI
OA1
2
DAT
A_
SGPI
OA1
3
DAT
A_
SGPI
OA2
0
DAT
A_
SGPI
OA1
4
DAT
A_
S
G
P
IOA2
3
NVDDL
VSS
DAT
A_
S
G
P
IOA1
5
DAT
A_
SGPI
OA1
6
DAT
A_
SGPI
OA2
1
DAT
A_
S
G
P
IOA1
7
NVDDL
VSS
DAT
A_
S
G
P
IOA1
8
DAT
A_
S
G
P
IOA1
9
IR
Q3_
B
_KR_B_
RETRY_
B_SGPI
OC3
IR
Q4
_B
_
A
T
2
_S
GP
IO
C
4
IR
Q
1
_B
_R
S
V
_B
_S
G
P
IO
C
1
S
G
P
IOC7_
IR
QOUT
_
B
_L
WP
0
BB_
B
_
VF
2
_
IW
P
3
B
G
_
B
_V
F
0
_L
W
P
1
NVDDL
VS
S
BR_
B_
VF
1
_
IW
P
2
RD_
W
R
_
B
OE
_B
TE
A
_
B
IR
Q2_
B
_CR_B
_
SGPI
OC2
IR
Q
0
_
B
_S
G
P
IO
C
0
WE
_
B
_
A
T
0
WE
_
B
_
A
T
1
WE
_
B
_
A
T
2
WE
_
B
_
A
T
3
VSS
NVDDL
CS
0
_
B
C
S
1_B
CS
2
_
B
C
S
3_B
BURST_
B
I_
B
_S
T
S
_B
TS
IZ
O
TS
IZ
1
NVDDL
VSS
TS
_
B
TA_B
BDI
P
_
B
B0E
P
EE
EPE
E
NVDDL
VDD2
CL
KOUT
VSS
E
NGCL
K
_
B
UCL
K
VDDH5
VDD2
QVDDL
VSS
QVDDL
IRQ5_B_SGPIOC5_MODCK1
IRQ6_B_MODCK2
IRQ7_B_MODCK3
HRESET_B
RSTCONF_B_TEXP
SRESET_B
PORESET_B_TRST_B
VSS
EXTCLK
VSS
VDDSYN
XFC
VSSSYN
EXTAL
XTAL
KAPWR
NVDDL
VDDF
A_CNRXO
VSSF
A_CNTXO
VFLASH
A_PCS0_SS_B_QGPIO0
PULLSEL
A_PCS1_QGPIO1
A_TXD2_QGPO2
A_PCS2_QGPIO2
A_RXD2_QPI2
B_RXD1_QGP01
A_RXD1_QPI1
A_MOSI_QGPIO5
A_PCS3_QGPIO3
A_MISO_QGPIO4
A_SCK_QGPIO6
B_PCS2_QGPIO2
B_RXD2_J1850_RX
A_TXD1_QGPO1
B_TXD2_QGPO2
B_TXD1_QGP01
B_ECK
B_SCK_QGPIO6
B_MOSI_QGPIO5
B_MISO_QGPIO4
B_PCS3_J1850_TX
B_PCS1_QGPIO1
B_PCS0_SS_B_QGPIO0
VFLS1_MPIO32B4
VDDH1
VFLS0_MPIO32B3
VF2_MPIO32B2
VSS
NVDDL
VF1_MPIO32B1
VF0_MPIO32B0
MPWM4_MPIO32B5
MPWM19
32KCLKOUT_MPIO32B15
C_CNRX0_MPIO32B14
C_CNTX0_MPIO32B13
MPWM21_MPIO32B12
MPWM20_MPIO32B11
MDA15
MDA14
MPWM16
MPWM3
MPWM2
MPWM1
MPWM0
MDA31
MDA30
MDA29
MDA28
MDA27
MDA13
MDA12
MDA11
MPWM18
MPWM17
B_T2CLK
B_TPUCH1
B_TPUCH0
MPWM5_MPIO32B6
VSS
VDD3
VSS
VS
S
B_
T
P
UCH2
B_
T
P
UCH15
B_
T
P
UCH14
B_
TP
UCH1
3
B_
TPUCH1
2
B_
T
P
UCH1
1
B_
TPUCH1
0
B_
TPUCH9
B_
T
P
UCH8
B_
TPUCH7
B_
T
P
UCH6
B_
T
P
UCH5
B_
T
P
UCH4
B_
TPUCH3
A_
T
P
UCH1
A_
TPUCH0
A_
T
2
CL
K
A_
TPUCH1
5
A_
T
P
UCH14
A_
TP
UCH1
3
A
_
T
PUCH1
2
A_
TP
UCH1
1
A
_
T
PUCH1
0
A_
T
P
UCH9
A_
TPUCH8
A_
T
P
UCH7
A_
TPUCH6
A_
T
P
UCH5
A_
T
P
UCH4
A_
TPUCH3
A_
T
P
UCH2
ETRI
G
1
ETR
IG
2
QVDDL
VSS
QVDDL
VDDH2
B_
AN5
9_
P
QA7
B_
AN5
8_
P
QA6
B_
AN5
7_
P
QA5
B_
AN5
6_
P
QA4
B_
AN5
5
_
PQA3
B_
AN5
4
_
MA2
_
P
QA2
B_
AN5
3
_
MA1
_
P
QA1
B_
AN5
2
_
MA0
_
P
QA0
B_
AN5
1
_
P
Q
B7
B_
AN5
0
_
P
Q
B6
B_
AN4
9
_
P
Q
B5
B_
AN4
8
_
P
Q
B4
B_
AN3
_
ANZ_
P
QB3
B_
AN2
_ANY_
P
Q
B2
B_
AN1_
ANX_
P
Q
B1
B_AN0
_
ANW
_
P
QB0
V
SSA
VDDA
A_
AN5
9
_
P
QA7
A_
AN5
8_
P
QA6
A_
AN5
7
_
P
QA5
A_
AN5
6_
P
QA4
A_
AN5
5
_
PQA3
A_
AN5
4
_
MA2
_
P
QA2
A_
AN5
3
_
MA1
_
P
QA1
A_
AN5
2
_
MA0
_
P
QA0
A_
AN5
1
_
PQB7
A_
AN5
0
_
PQB6
A_
AN4
9
_
P
Q
B5
A_
AN4
8_
P
Q
B4
A_
AN3
_
ANZ
_
P
QB3
A_
AN2
_ANY_
P
Q
B2
AM
UX_0
AM
UX_
1
AM
UX_2
AM
UX_
3
AM
UX_
4
AMUX_
5
AM
UX_
6
AMUX_
7
VRL
A
LTR
EF
VRH
A_
AN1
_
ANX_P
Q
B1
A_AN0
_
ANW
_
P
QB
0
NVDDL
VS
S
B_CNR
X
0
VDDH3
VDD4