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參數(shù)資料
| 型號： | MPC566MZP56 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 1M FLASH 56MHZ 388-PBGA |
| 標準包裝： | 40 |
| 系列： | MPC5xx |
| 核心處理器： | PowerPC |
| 芯體尺寸： | 32-位 |
| 速度： | 56MHz |
| 連通性： | CAN，EBI/EMI，SCI，SPI，UART/USART |
| 外圍設備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 56 |
| 程序存儲器容量： | 1MB（1M x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 36K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.5 V ~ 2.7 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 40x10b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 388-BBGA |
| 包裝： | 托盤 |
6
MPC565/MPC566 Product Brief
MOTOROLA
Detailed Feature List
1.2.11.2 22-Channel Modular I/O System (MIOS14)
22-channel MIOS timer (MIOS14)
Six modulus counter submodules (MCSM)
— Four additional MCSM submodules compared to MIOS1
10 double action submodules (DASM).
12 dedicated PWM submodules (PWMSM)
— Four additional PWM submodules compared to MIOS1 (shared with MIOS GPIO pins)
MIOS real-time clock submodule (MRTCSM) provides low power clock/counter
— Requires external 32-KHz crystal
— Uses four pins: two for 32-KHz crystal, two for power/ground.
1.2.12 Two Enhanced Queued Analog-to-Digital Converter
Modules (QADC64E)
Two enhanced queued analog to digital converters (QADC64E A, QADC64E B) with AMUXes
for 40 total analog channels.
10 bit A/D converter with internal sample/hold
— Typical conversion time is 4 s (250-Kbyte samples/sec)
— Two conversion command queues of variable length
Automated queue modes initiated by:
— External edge trigger/level gate
— Software command
— Periodic/interval timer, assignable to both queue 1 and 2
64 result registers in each QADC64E module
— Output data is right or left justified, signed or unsigned
Synchronized clock mode allows both QADC64Es to see the same conversion clock. This allows
the two modules to look like one large QADC with four queues.
Conversions alternate reference (ALTREF) pin. This pin can be connected to a different reference
voltage
1.2.13 Three CAN 2.0B Controller (TouCAN) Modules
Three TouCAN modules (TouCAN_A, TouCAN_B, and TouCAN_C)
16 message buffers each, programmable I/O modes
Maskable interrupts
Programmable loopback for self-test operation
Independent of the transmission medium (external transceiver is assumed)
Open network architecture, multimaster concept
High immunity to EMI
Short latency time for high-priority messages
Low power sleep mode, with programmable wake up on bus activity
TouCAN_C pins shared with MIOS14 GPIO pins
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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