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參數(shù)資料
| 型號： | MPC740ARX233LX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 233 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件頁數(shù)： | 3/44頁 |
| 文件大小： | 280K |
| 代理商： | MPC740ARX233LX |
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MPC750A RISC Microprocessor Hardware Specications
11
Electrical and Thermal Characteristics
Figure 3 provides the SYSCLK input timing diagram.
Figure 3. SYSCLK Input Timing Diagram
4
SYSCLK duty cycle
measured at 1.4V
40
60
40
60
40
60
%
3
SYSCLK jitter
—
±150
—
±150
—
±150
ps
4
Internal PLL relock
time
—
100
—
100
—
100
s5
Notes:
1.
Caution: The SYSCLK frequency and PLL_CFG[0–3] settings must be chosen such that the resulting
SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective
maximum or minimum operating frequencies. Refer to the PLL_CFG[0–3] signal description in Section 1.8.1,
“PLL Configuration,” for valid PLL_CFG[0–3] settings
2. Rise and fall times for the SYSCLK input are measured from 0.4 to 2.4V.
3. Timing is guaranteed by design and characterization.
4. The total input jitter (short term and long term combined) must be under ±150 ps.
5. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time
required for PLL lock after a stable Vdd and SYSCLK are reached during the power-on reset sequence. This
specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode.
Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during
the power-on reset sequence.
Table 8. Clock AC Timing Specifications (Continued)
At recommended operating conditions (See Table 3)
Num
Characteristic
200 MHz
233 MHz
266 MHz
Unit
Notes
Min
Max
Min
Max
Min
Max
VM
VM = Midpoint Voltage (1.4V)
2
3
CVIL
CVIH
1
SYSCLK
VM
4
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