MOTOROLA
MPC7410 RISC Microprocessor Hardware Specifications
37
System Design Information
by the input receivers on the MPC7410 or by other receivers in the system. These signals can be pulled up
through weak (10-k
) pull-up resistors by the system, address bus driven mode can be enabled (see the
MPC7410 RISC Microprocessor Family Users’ Manual for more information on this mode), or these
signals may be otherwise driven by the system during inactive periods of the bus to avoid this additional
power draw. The snooped address and transfer attribute inputs are: A[0:31], AP[0:3], TT[0:4], CI, WT, and
GBL.
In systems where GBL is not connected and other devices may be asserting TS for a snoopable transaction
while not driving GBL to the processor, we recommend that a strong (1 k
) pull-up resistor be used on
GBL. Note that the MPC7410 will only snoop transactions when GBL is asserted.
The data bus input receivers are normally turned off when no read operation is in progress and, therefore,
do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require
pull-ups, or that those signals be otherwise driven by the system during inactive periods by the system. The
data bus signals are: DH[0:31], DL[0:31], and DP[0:7].
If address or data parity is not used by the system, and the respective parity checking is disabled through
HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and
should be left unconnected by the system. If parity checking is disabled through HID0, and parity generation
is not required by the MPC7410 (note that the MPC7410 always generates parity), then all parity pins may
be left unconnected by the system.
The L2 interface does not normally require pull-up resistors.
1.8.7
JTAG Configuration Signals
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification, but is provided on all processors that implement the PowerPC architecture.
While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more
reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset.
Because the JTAG interface is also used for accessing the common on-chip processor (COP) function,
simply tying TRST to HRESET is not practical.
The COP function of these processors allows a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG port of the processor, with some additional status monitoring
signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control
the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers,
power supply failures, or push-button switches, then the COP reset signals must be merged into these signals
with logic.
The arrangement shown in
Figure 23 allows the COP port to independently assert HRESET or TRST, while
ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not be used,
TRST should be tied to HRESET through a 0-
isolation resistor so that it is asserted when the system reset
signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during power-on. While
Motorola recommends that the COP header be designed into the system as shown in
Figure 23, if this is not
possible, the isolation resistor will allow future access to TRST in the case where a JTAG interface may need
to be wired onto the system in debug situations.
The COP header shown in
Figure 23 adds many benefits—breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features are possible through this interface—and
can be as inexpensive as an unpopulated footprint for a header to be added when needed.