參數(shù)資料
型號: MPC7410RX450LX
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 450 MHz, RISC PROCESSOR, CBGA360
封裝: 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁數(shù): 37/44頁
文件大?。?/td> 885K
代理商: MPC7410RX450LX
42
MPC7410 RISC Microprocessor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Document Revision History
1.9 Document Revision History
Table 18 provides a revision history for this hardware specification.
1.10 Ordering Information
Figure 28 provides the Motorola part numbering nomenclature for the MPC7410. Note that the individual
part numbers correspond to a maximum processor core frequency. For available frequencies, contact your
local Motorola sales office. In addition to the processor frequency, the part numbering scheme also consists
of a part modifier and application modifier. The part modifier indicates any enhancement(s) in the part from
the original production design. The bus divider may specify special bus frequencies or application
conditions. Each part number also contains a revision code. This refers to the die mask revision number and
is specified in the part numbering scheme for identification purposes only.
Table 18. Document Revision History
Document Revision
Substantive Change(s)
Rev 0
Initial release
Rev 0.1
Minor updates
Rev 0.2
Corrected Section 1.3 General Parameters - Technology from 0.13 m to 0.18
m
.
Updated Table 7 - adds power consumption numbers; adds note on estimated
decrease w/o AltiVec.
Updated Table 8 - adds minimun values for Processor frequency and VCO
frequency.
Updated Table 9: Input Setup, Output Valid Times, Output Hold Times, SYSCLK
to Output High Impedance.
Updated Table 11: L2SYNC_IN to high impedance.
Updated Figure 17 - Mechanical Dimensions, adds capacitor pad dimensions.
Rev 0.3
Added 3.3 V support on the processor bus (BVSEL).
Table 7 - update Typical and Maximum power numbers for Full-On Mode in.
Removed note 4. Reworded notes 2 and 3.
Table 9, Note 2 - removed reference to application note.
Figure 17 - corrected side view datum A to now be datum C.
Section 1.8.7 - added CI and WT to transfer attribute signals requiring pull-ups.
Section 1.8.7 - added 1 k
pull-up recommendation to GBL when GBL is not
connected.
Table 2 - added pull-down resistance necessary for internally pulled-up voltage
select pins. Added 3.3 V support for BVSEL.
Table 13 - added note 14 for BVSEL, L2VSEL, and TRST pins to address
pull-down resistance necessary for these internally pulled-up pins to recognize
a low signal.
Table 6 - lowered 2.5 V CVIH from 2.2 V to 2.0 V to be compatible with VOH of
the MPC107. Added support for 3.3 V processor bus.
Table 15 - modified note 1, use L2CR[L2SL] for L2CLK freq. less than 150 MHz.
Table 8 - revised note 2 discussing for 3.3V bus voltage support.
Table 14 - added note 5, do not use PLL-off during power-up sequence.
Table 11 - update Output Hold Times (tL2CHOX)
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