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參數(shù)資料
| 型號： | MPC745BPX350LE |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 350 MHz, RISC PROCESSOR, PBGA255 |
| 封裝： | 21 X 21 MM, PLASTIC, BGA-255 |
| 文件頁數(shù)： | 29/52頁 |
| 文件大?。?/td> | 1276K |
| 代理商： | MPC745BPX350LE |
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MOTOROLA
MPC755 RISC Microprocessor Hardware Specifications
35
System Design Information
1.8.2
PLL Power Supply Filtering
The AVDD and L2AVDD power signals are provided on the MPC755 to provide power to the clock
generation PLL and L2 cache DLL, respectively. To ensure stability of the internal clock, the power supplied
to the AVDD input signal should be filtered of any noise in the 500 kHz to 10 MHz resonant frequency range
of the PLL. A circuit similar to the one shown in Figure 21 using surface mount capacitors with minimum
Effective Series Inductance (ESL) is recommended. Consistent with the recommendations of Dr. Howard
Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small
capacitors of equal value are recommended over a single large value capacitor.
The circuit should be placed as close as possible to the AVDD pin to minimize noise coupled from nearby
circuits. An identical but separate circuit should be placed as close as possible to the L2AVDD pin. It is often
possible to route directly from the capacitors to the AVDD pin, which is on the periphery of the 360 BGA
footprint, without the inductance of vias. The L2AVDD pin may be more difficult to route, but is
proportionately less critical.
FIgure 21 shows the PLL power supply filter circuit.
Figure 21. PLL Power Supply Filter Circuit
1.8.3
Decoupling Recommendations
Due to the MPC755 dynamic power management feature, large address and data buses, and high operating
frequencies, the MPC755 can generate transient power surges and high frequency noise in its power supply,
especially while driving large capacitive loads. This noise must be prevented from reaching other
components in the MPC755 system, and the MPC755 itself requires a clean, tightly regulated source of
power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each
VDD, OVDD, and L2OVDD pin of the MPC755. It is also recommended that these decoupling capacitors
receive their power from separate VDD, (L2)OVDD, and GND power planes in the PCB, utilizing short
traces to minimize inductance.
These capacitors should have a value of 0.01 F or 0.1 F. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0508 or 0603 orientations where
connections are made along the length of the part.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD, L2OVDD, and OVDD planes, to enable quick recharging of the smaller chip capacitors.
These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick
response time necessary. They should also be connected to the power and ground planes through two vias
to minimize inductance. Suggested bulk capacitors:100–330 F (AVX TPS tantalum or Sanyo OSCON).
1.8.4
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level through a resistor. Unused active low inputs should be tied to OVDD. Unused active high inputs should
be connected to GND. All NC (no connect) signals must remain unconnected.
VDD
AVDD (or L2AVDD)
10
2.2 F
GND
Low ESL Surface Mount Capacitors
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