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| 型號： | MPC750ARX200TX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 3.20 MM HIEGHT, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 27/44頁 |
| 文件大小： | 280K |
| 代理商： | MPC750ARX200TX |
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MPC750A RISC Microprocessor Hardware Specications
33
System Design Information
Table 18 provides sample core-to-L2 frequencies.
1.8.2 PLL Power Supply Filtering
The AVdd and L2AVdd power signals are provided on the MPC750 to provide power to the clock
generation phase-locked loop and L2 cache delay-locked loop respectively. To ensure stability of the
internal clock, the power supplied to the AVdd input signal should be ltered using a circuit similar to the
one shown in Figure 18. The circuit should be placed as close as possible to the AVdd pin to ensure it lters
out as much noise as possible. An identical but separate circuit should be placed as close as possible to the
L2AVdd pin.
Figure 18. PLL Power Supply Filter Circuit
1.8.3 Decoupling Recommendations
Due to the MPC750’s dynamic power management feature, large address and data buses, and high
operating frequencies, the MPC750 can generate transient power surges and high frequency noise in its
power supply, especially while driving large capacitive loads. This noise must be prevented from reaching
other components in the MPC750 system, and the MPC750 itself requires a clean, tightly regulated source
of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at
each Vdd and OVdd pin (and L2OVdd for the 360 CBGA) of the MPC750. It is also recommended that
these decoupling capacitors receive their power from separate Vdd, OVdd, and GND power planes in the
PCB, utilizing short traces to minimize inductance.
Table 18. Sample Core-to-L2 Frequencies
Core Frequency in
MHz
÷1
÷1.5
÷2
÷2.5
÷3
200
133.3
100
80
—
208.3
208
138.6
104
83.3
—
210
140
105
84
—
220
146.6
110
88
—
225
150
112.5
90
—
233.3
155.5
116.6
93.3
—
240
160
120
96
80
266
177.3
133
106.4
88.6
Note: The core and L2 frequencies are for reference only. Some congurations may select core or L2
frequencies which are not useful, not supported, or not tested for by the MPC750; see
Section 1.4.2.4, “L2 Clock AC Specications,” for valid L2CLK frequencies. The L2CR[L2SL]
bit should be set for L2CLK frequencies less than 110 MHz.
Vdd
AVdd (or L2AVdd)
10
10 F
0
.1 F
GND
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