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參數(shù)資料
| 型號： | MPC750PRX366RE |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 366 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 14/24頁 |
| 文件大小： | 543K |
| 代理商： | MPC750PRX366RE |
XPC750P RISC Microprocessor Hardware Specications
21
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
System Design Information
The XPC750P generates the clock for the external L2 synchronous data SRAMs by dividing the core clock
frequency of the XPC750P. The divided-down clock is then phase-adjusted by an on-chip delay-lock-loop
(DLL) circuit and should be routed from the XPC750P to the external RAMs. A separate clock output,
L2SYNC_OUT is sent out half the distance to the SRAMs and then returned as an input to the DLL on pin
L2SYNC_IN so that the rising-edge of the clock as seen at the external RAMs can be aligned to the clocking
of the internal latches in the L2 bus interface.
The core-to-L2 frequency divisor for the L2 PLL is selected through the L2CLK bits of the L2CR register.
Generally, the divisor must be chosen according to the frequency supported by the external RAMs, the
frequency of the XPC750P core, and the phase adjustment range that the L2 DLL supports. Table 15. shows
various example L2 clock frequencies that can be obtained for a given set of core frequencies.
0001
7.5x
2x
250
(500)
300
(600)
375
(750)
1100
8x
2x
266
(533)
320
(640)
400
(800)
0011
PLL off/bypass
PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied
1111
PLL off
PLL off, no core clocking occurs
Notes:
1. PLL_CFG[03] settings not listed are reserved.
2. The sample bus-to-core frequencies shown are for reference only. Some PLL congurations may
select bus, core, or VCO frequencies which are not useful, not supported, or not tested for by the
XPC750P; see Section 1.4.2.1, Clock AC Specications, for valid SYSCLK and VCO frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is
disabled, and the bus mode is set for 1:1 mode operation. This mode is intended for factory use only.
Note: The AC timing specications given in this document do not apply in PLL-bypass mode.
4. In clock-off mode, no clocking occurs inside the XPC750P regardless of the SYSCLK input.
Table 15. Sample Core-to-L2 Frequencies
Core Frequency
in MHz
1
1.5
2
2.5
3
300
200
150
120
100
333
222
167
133
111
366
244
183
146
122
400
266
200
150
133
Note: The core and L2 frequencies are for reference only. Some congurations may select core or
L2 frequencies which are not useful, not supported, or not tested for by the XPC750P; see
Section 1.4.2.4, L2 Clock AC Specications, for valid L2CLK frequencies. The L2CR[L2SL]
bit should be set for L2CLK frequencies less than 110 MHz.
Table 14. XPC750P Microprocessor PLL Configuration (Continued)
PLL_CFG
[03]
Sample Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core-to
VCO
Multiplier
Bus
33.3
MHz
Bus
40 MHz
Bus
50 MHz
Bus
66.6
MHz
Bus
75 MHz
Bus
83.3
MHz
Bus
100
MHz
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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