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參數(shù)資料
| 型號： | MPC8247CVRTIEA |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 34/61頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU POWERQUICC II 516-PBGA |
| 特色產(chǎn)品： | MPC8247 Communications Processors |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | MPC82xx |
| 處理器類型： | 32-位 MPC82xx PowerQUICC II |
| 速度： | 400MHz |
| 電壓： | 1.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 516-BBGA |
| 供應(yīng)商設(shè)備封裝： | 516-FPBGA（27x27） |
| 包裝： | 托盤 |
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MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
4
Freescale Semiconductor
Overview
— Floating-point unit (FPU) supports floating-point arithmetic
— Support for cache locking
Low-power consumption
Separate power supply for internal logic (1.5 V) and for I/O (3.3 V)
Separate PLLs for G2_LE core and for the communications processor module (CPM)
— G2_LE core and CPM can run at different frequencies for power/performance optimization
— Internal core/bus clock multiplier that provides ratios 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1,
5.5:1, 6:1, 7:1, 8:1
— Internal CPM/bus clock multiplier that provides ratios 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1, 8:1
ratios
64-bit data and 32-bit address 60x bus
— Bus supports multiple master designs—up to two external masters
— Supports single transfers and burst transfers
— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
60x-to-PCI bridge
— Programmable host bridge and agent
— 32-bit data bus, 66 MHz, 3.3 V
— Synchronous and asynchronous 60x and PCI clock modes
— All internal address space available to external PCI host
— DMA for memory block transfers
– PCI-to-60x address remapping
System interface unit (SIU)
— Clock synthesizer
— Reset controller
— Real-time clock (RTC) register
— Periodic interrupt timer
— Hardware bus monitor and software watchdog timer
— IEEE 1149.1 JTAG test access port
Eight bank memory controller
— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash, and other
user-definable peripherals
— Byte write enables
— 32-bit address decodes with programmable bank size
— Three user-programmable machines, general-purpose chip-select machine, and page mode
pipeline SDRAM machine
— Byte selects for 64-bit bus width (60x)
— Dedicated interface logic for SDRAM
Disable CPU mode
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| MPC8247CZQ | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MPC8272 PowerQUICC II Family Hardware Specifications |
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| MPC8247CZQE | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
| MPC8247CZQI | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
| MPC8247CZQM | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
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