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參數(shù)資料
| 型號： | MPC8260AZUPIBB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, RISC PROCESSOR, PBGA480 |
| 封裝： | 37.50 X 37.50 MM, TBGA-480 |
| 文件頁數(shù)： | 7/40頁 |
| 文件大?。?/td> | 527K |
| 代理商： | MPC8260AZUPIBB |
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MOTOROLA
MPC8260 (HiP3) Hardware Specications
15
Electrical and Thermal Characteristics
Table 10 lists SIU output characteristics.
Activating data pipelining (setting BRx[DR] in the memory controller)
improves the AC timing. When data pipelining is activated, sp12 can be
used for data bus setup even when ECC or PARITY are used. Also, sp33a
can be used as the AC specication for DP signals.
Figure 8 shows TDM input and output signals.
Figure 8. TDM Signal Diagram
Figure 9 shows the interaction of several bus signals.
Table 10. AC Characteristics for SIU Outputs1
1 Output specications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the
signal. Timings are measured at the pin.
Spec Number
Characteristic
Max Delay (ns) Min Delay (ns)
Max
Min
66 MHz
sp31
sp30
PSDVAL/TEA/TA
10
0.5
sp32
sp30
ADD/ADD_atr./BADDR/CI/GBL/WT
8
0.5
sp33a
sp30
Data bus
8
0.5
sp33b
sp30
DP
12
0.5
sp34
sp30
memc signals/ALE
6
0.5
sp35
sp30
all other signals
7.5
0.5
Serial CLKin
TDM input signals
TDM output signals
sp20
sp21
sp40/sp41
Note: There are four possible TDM timing conditions:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
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| MPC8260AZUPJDB | 功能描述:微處理器 - MPU POWERQUICC II HIP4 REV B RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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