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參數(shù)資料
| 型號(hào)： | MPC8260AZUPJDB |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 40/50頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU POWERQUICC II 480-TBGA |
| 標(biāo)準(zhǔn)包裝： | 21 |
| 系列： | MPC82xx |
| 處理器類型： | 32-位 MPC82xx PowerQUICC II |
| 速度： | 300MHz |
| 電壓： | 2V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 480-LBGA |
| 供應(yīng)商設(shè)備封裝： | 408-TBGA（37.5x37.5） |
| 包裝： | 托盤 |
| 配用： | MPC8260ADS-TCOM-ND - BOARD DEV ADS POWERQUICC II |
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MPC8260A PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2.0
Freescale Semiconductor
45
Pinout
PD21/TXD4/FCC1_UT16_RXD3/L1RXD0A2/L1RXDA2
AH132
PD22/RXD4/FCC1_UT16_TXD5/L1TXD0A2/L1TXDA2
AJ122
PD23/RTS3/TENA3/FCC1_UT16_RXD4/L1RSYNCD1
AE122
PD24/TXD3/FCC1_UT16_RXD5/L1RXDD1
AF102
PD25/RXD3/FCC1_UT16_TXD6/L1TXDD1
AG92
PD26/RTS2/TENA2/FCC1_UT16_RXD6/L1RSYNCC1
AH82
PD27/TXD2/FCC1_UT16_RXD7/L1RXDC1
AG72
PD28/RXD2/FCC1_UT16_TXD7/L1TXDC1
AE42
PD29/RTS1/TENA1/FCC1_UTM_RXADDR3/FCC1_UTS_RXADDR3/
FCC1_UTM_RXCLAV2/FCC2_UTM_RXADDR4
AG12
PD30/FCC2_UTM_TXENB/FCC2_UTS_TXENB/TXD1
AD42
PD31/RXD1
AD22
VCCSYN
AB3
VCCSYN1
B9
GNDSYN
AB1
CLKIN21,3
AE11
SPARE44
U5
PCI_MODE1,5
AF25
SPARE64
V4
THERMAL06
AA1
THERMAL16
AG4
I/O power
AG21, AG14, AG8, AJ1, AJ2, AH1, AH2,
AG3, AF4, AE5, AC27, Y27, T27, P27,
K26, G27, AE25, AF26, AG27, AH28,
AH29, AJ28, AJ29, C7, C14, C16, C20,
C23, E10, A28, A29, B28, B29, C27,
D26, E25, H3, M4, T3, AA4, A1, A2, B1,
B2, C3, D4, E5
Core Power
U28, U29, K28, K29, A9, A19, B19, M1,
M2, Y1, Y2, AC1, AC2, AH19, AJ19,
AH10, AJ10, AJ5
Ground
AA5, AF21, AF14, AF8, AE7, AF11,
AE17, AE23, AC26, AB25, Y26, V25,
T26, R25, P26, M25, K27, H25, G26,
D7, D10, D14, D16, D20, D23, C9, E11,
E13, E15, E19, E22, B3, G5, H4, K5,
M3, P5, T4, Y5, AA2, AC3
1 MPC8265 and MPC8266 only.
2 The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input. To prevent excessive
DC current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs.
Table 21. Pinout List (continued)
Pin Name
Ball
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