參數(shù)資料
型號(hào): MPC8260AZUPJDB
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 300 MHz, RISC PROCESSOR, PBGA480
封裝: 37.50 X 37.50 MM, TBGA-480
文件頁(yè)數(shù): 34/40頁(yè)
文件大?。?/td> 527K
代理商: MPC8260AZUPJDB
4
MPC8260 (HiP3) Hardware Specications
MOTOROLA
Features
— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
— Three fast communications controllers (two on the MPC8255) supporting the following
protocols:
– 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent
interface (MII)
– ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5,
AAL1, AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR trafc types, up to 16 K external
connections
– Transparent
– HDLC—Up to T3 rates (clear channel)
— Two multichannel controllers (MCCs) (only MCC2 on the MPC8255)
– Each MCC handles 128 serial, full-duplex, 64-Kbps data channels. Each MCC can be split
into four subgroups of 32 channels each.
– Almost any combination of subgroups can be multiplexed to single or multiple TDM
interfaces up to four TDM interfaces per MCC
— Four serial communications controllers (SCCs) identical to those on the MPC860, supporting
the digital portions of the following protocols:
– Ethernet/IEEE 802.3 CDMA/CS
– HDLC/SDLC and HDLC bus
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART
– Binary synchronous (BISYNC) communications
– Transparent
— Two serial management controllers (SMCs), identical to those of the MPC860
– Provide management for BRI devices as general circuit interface (GCI) controllers in time-
division-multiplexed (TDM) channels
– Transparent
– UART (low-speed operation)
— One serial peripheral interface identical to the MPC860 SPI
— One inter-integrated circuit (I2C) controller (identical to the MPC860 I2C controller)
– Microwire compatible
– Multiple-master, single-master, and slave modes
— Up to eight TDM interfaces (4 on the MPC8255)
– Supports two groups of four TDM channels for a total of eight TDMs
– 2,048 bytes of SI RAM
– Bit or byte resolution
– Independent transmit and receive routing, frame synchronization
– Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN
primary rate, Motorola interchip digital link (IDL), general circuit interface (GCI), and
user-dened TDM serial interfaces
— Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs,
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