參數(shù)資料
型號(hào)： MPC8264AZUPIBX
廠商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 300 MHz, RISC PROCESSOR, PBGA480
封裝： 37.50 X 37.50 MM, 1.27 MM PITCH, TBGA-480
文件頁(yè)數(shù)： 30/111頁(yè)
文件大?。?/td> 1007K
代理商： MPC8264AZUPIBX
MOTOROLA
MPC826xA (HiP4) Family Hardware Specications
25
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Clock Conguration Modes
1010_010
100 MHz
2
200 MHz
3
300 MHz
3/6
66/33 MHz
1010_011
100 MHz
2
200 MHz
3.5
350 MHz
3/6
66/33 MHz
1010_100
100 MHz
2
200 MHz
4
400 MHz
3/6
66/33 MHz
1011_000
100 MHz
2.5
250 MHz
2
200 MHz
4/8
62/31 MHz
1011_001
100 MHz
2.5
250 MHz
2.5
250 MHz
4/8
62/31MHz
1011_010
100 MHz
2.5
250 MHz
3
300 MHz
4/8
62/31 MHz
1011_011
100 MHz
2.5
250 MHz
3.5
350 MHz
4/8
62/31 MHz
1011_100
100 MHz
2.5
250 MHz
4
400 MHz
4/8
62/31 MHz
1100_0004
66MHz
2
133MHz
Bypass
66MHz
2/4
66/33 MHz
1100_0014
66MHz
2.5
166MHz
Bypass
66MHz
3/6
55/28 MHz
1100_0104
66MHz
3
200MHz
Bypass
66MHz
3/6
66/33 MHz
1 Input clock frequency is given only for the purpose of reference. User should set MODCK_H–MODCK_L so that
the resulting conguration does not exceed the frequency rating of the user’s part.
Example. If a part is rated at 266 MHz CPU, 200 MHz CPM, and 66 MHz bus, any of the following are possible
(note that the three input clock frequencies are only three of many possible input clock frequencies):
1. 66 MHz input clock, MODCK_H–MODCK_L[0111–011] (with a core multiplication factor of 4 and a CPM
multiplication factor of 3), and PCI_MODCK = 0 (see note 2 below). The resulting conguration equals the
part’s maximum possible frequencies of 266 MHz CPU, 200 MHz CPM, 66 MHz 60x bus, and a PCI
frequency of 66 MHz.
2. 50 MHz input clock, MODCK_H–MODCK_L[0111–011], and PCI_MODCK = 0 (see note 2below) to
achieve a conguration of 200 MHz CPU, 150 MHz CPM, 50 MHz 60x bus, and a PCI frequency of 50 MHz.
3. 40 MHz input clock, MODCK_H–MODCK_L[0010–000], and PCI_MODCK = 0 (see note 2 below) to
achieve a conguration of 200 MHz CPU, 160 MHz CPM, 40 MHz 60x bus, and a PCI frequency of 40 MHz.
Note that with each of the examples, any one of several values for MODCK_H–MODCK_L could possibly be
used as long as the resulting conguration does not exceed the part’s rating.
2 The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic ‘1’), the PCI frequency is
divided by 2 (33 instead of 66 MHz, etc.).
3 In this mode, PCI_MODCK must be “0”.
4 In this mode the Core PLL is bypassed (core frequency equals to bus frequency; for debug purpose only).
Table 18. Clock Default Congurations in PCI Agent Mode (MODCK_HI = 0000)1
MODCK[1–3]2
Input Clock
Frequency
CPM
Multiplication
Factor3
CPM
Frequency
Core
Multiplication
Factor
Core
Frequency4
Bus Division
Factor
60x Bus
Frequency5
000
66/33 MHz
2/4
133 MHz
2.5
166 MHz
2
66 MHz
001
66/33 MHz
2/4
133 MHz
3
200 MHz
2
66 MHz
010
66/33 MHz
3/6
200 MHz
3
200 MHz
3
66 MHz
011
66/33 MHz
3/6
200 MHz
4
266 MHz
3
66 MHz
Table 17. Clock Conguration Modes in PCI Host Mode (Continued)
MODCK_H –
MODCK[1–3]
Input Clock
Frequency1
(Bus)
CPM
Multiplication
Factor
CPM
Frequency
Core
Multiplication
Factor
Core
Frequency
PCI Division
Factor2
PCI
Frequency2
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