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參數(shù)資料
| 型號： | MPC8275CZQSLDX |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 375 MHz, RISC PROCESSOR, PBGA516 |
| 封裝： | 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-516 |
| 文件頁數(shù)： | 14/80頁 |
| 文件大小： | 536K |
| 代理商： | MPC8275CZQSLDX |
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MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 1.8
Freescale Semiconductor
21
AC Electrical Characteristics
Figure 10 shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity).
Figure 10. Parity Mode Diagram
Figure 11 shows signal behavior in MEMC mode.
Figure 11. MEMC Mode Diagram
NOTE
Generally, all MPC8280 bus and system output signals are driven from the rising
edge of the input clock (CLKin). Memory controller signals, however, trigger on
four points within a CLKin cycle. Each cycle is divided by four internal ticks: T1,
T2, T3, and T4. T1 always occurs at the rising edge, and T3 at the falling edge, of
CLKin. However, the spacing of T2 and T4 depends on the PLL clock ratio
selected, as shown in Table 13.
CLKin
DATA bus, ECC, and PARITY mode
Pipeline mode—
DP mode output signal
sp13
sp10
sp14a
sp10
Pipeline mode—
sp10
DP mode input signal
sp14
sp10
DATA bus, ECC, and PARITY mode
DP mode input signal
input signals
sp30
sp33b
sp13a
CLKin
V_CLK
Memory controller signals
sp34/sp30
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