參數(shù)資料
型號(hào)： MPC8275ZQSLDX
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 375 MHz, RISC PROCESSOR, PBGA516
封裝： 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-516
文件頁數(shù)： 16/80頁
文件大?。?/td> 536K
代理商： MPC8275ZQSLDX
MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 1.8
Freescale Semiconductor
23
Clock Configuration Modes
7
Clock Configuration Modes
The MPC8280 has three clocking modes: local, PCI host, and PCI agent. The clocking mode is set according to three
input pins—PCI_MODE, PCI_CFG[0], PCI_MODCK—as shown in Table 15.
Input hold times
Boundary-scan data
TMS, TDI
tJTDXKH
tJTIXKH
10
—
ns
4, 7
Output valid times
Boundary-scan data
TDO
tJTKLDV
tJTKLOV
—
10
ns
5, 7
5. 7
Output hold times
Boundary-scan data
TDO
tJTKLDX
tJTKLOX
1
—
ns
5, 7
JTAG external clock to output high impedance
Boundary-scan data
TDO
tJTKLDZ
tJTKLOZ
1
10
ns
5, 6
1 All outputs are measured from the midpoint voltage of the falling/rising edge of t
TCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50-
Ω load. Time-of-flight delays
must be added for trace lengths, vias, and connectors in the system.
2 The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t((first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG
device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference
(K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input
signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock
reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
3 TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4 Non-JTAG signal input timing with respect to t
TCLK.
5 Non-JTAG signal output timing with respect to t
TCLK.
6 Guaranteed by design.
7 Guaranteed by design and device characterization.
Table 15. MPC8280 Clocking Modes
Pins
Clocking Mode
PCI Clock
Frequency Range
(MHZ)
Reference
PCI_MODE
PCI_CFG[0] PCI_MODCK 1
1
Determines PCI clock frequency range. Refer to Sections 7.2 and 7.3.
1
—
Local bus
—
0
PCI host
50–66
0
1
25–50
0
1
0
PCI agent
50–66
0
1
25–50
Table 14. JTAG Timings1 (continued)
Parameter
Symbol2
Min
Max
Unit
Notes
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