參數(shù)資料
型號(hào)： MPC8280CZUUPEX
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 450 MHz, RISC PROCESSOR, PBGA480
封裝： 37.50 X 37.50 MM, 1.55 MM HEIGHT, 1.27 MM PITCH, TBGA-480
文件頁(yè)數(shù)： 11/80頁(yè)
文件大?。?/td> 536K
代理商： MPC8280CZUUPEX
MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 1.8
Freescale Semiconductor
19
AC Electrical Characteristics
6.2 SIU AC Characteristics
Note the following points about the SIU AC characteristics:
CLKIN jitter and duty cycle. The CLKIN input to the MPC8280 should not exceed +/– 150 psec of jitter
(peak-to-peak). This represents total input jitter—the combination of short term (cycle-to-cycle) and long
term (cumulative). The duty cycle of CLKIN should not exceed the ratio of 40:60. The rise/file time of
CLKIN should adhere to the typical SDRAM device AC clock requirement of 1 V/ns to meet SDRAM AC
specs.
Spread spectrum clocking. Is allowed with 1% input frequency down-spread at maximum 60 KHz
modulation rate regardless of input frequency.
PCI AC timing. The MPC8280 meets the timing requirements of PCI Specification Revision 2.2. Refer to
Sections 7.2 and 7.3 and “Note: Tval (Output Hold)” to determine if a specific clock configuration is
compliant.
Activating data pipelining (setting BRx[DR] in the memory controller) improves the AC timing.
Table 11 lists SIU input characteristics.
Table 12 lists SIU output characteristics.
Table 11. AC Characteristics for SIU Inputs 1
1
Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are
measured at the pin.
Spec Number
Characteristic
Value (ns)
Setup
Hold
Setup
Hold
66 MHz
83 MHz
100 MHz
66 MHz
83 MHz
100 MHz
sp11
sp10
AACK/TA/TS/DBG/BG/BR/ARTRY/
TEA
6
5
3.5
0.5
sp12
sp10
Data bus in normal mode
5
4
3.5
0.5
sp13
sp10
Data bus in ECC and PARITY modes
7
5
3.5
0.5
sp13a
sp10
Pipeline mode—Data bus (with or without
ECC/PARITY)
5
4
2.5
0.5
sp14
sp10
DP pins
7
5
3.5
0.5
sp14a
sp10
Pipeline mode—DP pins
—
4
2.5
—
0.5
sp15
sp10
All other pins
5
4
3.5
0.5
Table 12. AC Characteristics for SIU Outputs 1
Spec Number
Characteristic
Value (ns)
Max
Min
Maximum Delay
Minimum Delay
66 MHz
83 MHz
100 MHz
66 MHz
83 MHz
100 MHz
sp31
sp30
PSDVAL/TEA/TA
76
5.5
1
11
sp32
sp30
ADD/ADD_atr./BADDR/CI/GBL/WT
8
6.5
5.5
1
sp33a
sp30
Data bus 2
6.5
5.5
0.7
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