參數(shù)資料
型號: MPC8280VVPX
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 300 MHz, RISC PROCESSOR, PBGA480
封裝: 37.5 X 37.5 MM, 1.55 MM, 1.27 MM PITCH, LEAD FREE, TBGA-480
文件頁數(shù): 13/83頁
文件大小: 618K
代理商: MPC8280VVPX
MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2
20
Freescale Semiconductor
AC Electrical Characteristics
This figure shows PIO and timer signals.
Figure 8. PIO and Timer Signal Diagram
6.2
SIU AC Characteristics
This table lists SIU input characteristics.
NOTE: CLKIN Jitter and Duty Cycle
The CLKIN input to the SoC should not exceed +/– 150 psec of jitter
(peak-to-peak). This represents total input jitter—the combination of short
term (cycle-to-cycle) and long term (cumulative). The duty cycle of CLKIN
should not exceed the ratio of 40:60. The rise/file time of CLKIN should
adhere to the typical SDRAM device AC clock requirement of 1 V/ns to
meet SDRAM AC specs.
NOTE: Spread Spectrum Clocking
Spread spectrum clocking is allowed with 1% input frequency down-spread
at maximum 60 KHz modulation rate regardless of input frequency.
NOTE: PCI AC Timing
The SoC meets the timing requirements of PCI Specification Revision 2.2.
See Section 7, “Clock Configuration Modes,” and “Note: Tval (Output
Hold)” to determine if a specific clock configuration is compliant.
Sys clk
PIO/IDMA/TIMER[TGATE assertion] input signals
IDMA output signals
sp22
sp23
sp42/sp43
TIMER(sp42/43)/ PIO(sp42a/sp43a)
sp42a/sp43a
output signals
sp42/sp43
TIMER input signal [TGATE deassertion]
sp22
sp23
Note: TGATE is asserted on the rising edge of the clock; it is deasserted on the falling edge.
(See note)
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