參數(shù)資料
型號(hào)： MPC8280ZUKHBX
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 233 MHz, RISC PROCESSOR, PBGA480
封裝： 37.50 X 37.50 MM, 1.55 MM HEIGHT, 1.27 MM PITCH, TBGA-480
文件頁(yè)數(shù)： 34/80頁(yè)
文件大?。?/td> 536K
代理商： MPC8280ZUKHBX
MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 1.8
4
Freescale Semiconductor
Overview
— High-performance (SPEC95 benchmark at 450 MHz; 855 Dhrystones MIPS at 450 MHz)
— Supports bus snooping for data cache coherency
— Floating-point unit (FPU)
Separate power supply for internal logic and for I/O
Separate PLLs for G2_LE core and for the CPM
— G2_LE core and CPM can run at different frequencies for power/performance optimization
— Internal core/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 6:1, 7:1, 8:1 ratios
— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1, 8:1 ratios
64-bit data and 32-bit address 60x bus
— Bus supports multiple master designs
— Supports single- and four-beat burst transfers
— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
— Supports data parity or ECC and address parity
32-bit data and 18-bit address local bus
— Single-master bus, supports external slaves
— Eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
60x-to-PCI bridge
— Programmable host bridge and agent
— 32-bit data bus, 66.67/83.3/100 MHz, 3.3 V
— Synchronous and asynchronous 60x and PCI clock modes
— All internal address space available to external PCI host
— DMA for memory block transfers
— PCI-to-60x address remapping
PCI bridge
— PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz
— On-chip arbitration
— Support for PCI-to-60x-memory and 60x-memory-to-PCI streaming
— PCI host bridge or periphera
l capabilities
— Includes 4 DMA channels for the following transfers:
– PCI-to-60x to 60x-to-PCI
– 60x-to-PCI to PCI-to-60x
– PCI-to-60x to PCI-to-60x
– 60x-to-PCI to 60x-to-PCI
— Includes all of the configuration registers (which are automatically loaded from the EPROM and used
to configure the MPC8280) required by the PCI standard as well as message and doorbell registers
— Supports the I2O standard
— Hot-swap friendly (supports the hot swap specification as defined by PICMG 2.1 R1.0 August 3, 1998)
— Support for 66.67/83.33/100 MHz, 3.3 V specification
— 60x-PCI bus core logic that uses a buffer pool to allocate buffers for each port
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