參數(shù)資料
型號(hào)： MPC8306VMACDCA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA369
封裝： 19 X 19 MM, 1.61 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MAPBGA-369
文件頁(yè)數(shù)： 58/76頁(yè)
文件大小： 474K
代理商： MPC8306VMACDCA
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
61
Clocking
22.1
System Clock Domains
As shown in Figure 42, the primary clock input (frequency) is multiplied up by the system phase-locked
loop (PLL) and the clock unit to create four major clock domains:
The coherent system bus clock (csb_clk)
The QUICC Engine clock (qe_clk)
The internal clock for the DDR controller (ddr_clk)
The internal clock for the local bus controller (lbc_clk)
The csb_clk frequency is derived from the following equation:
csb_clk = SYS_CLK_IN × SPMF
Eqn. 1
The csb_clk serves as the clock input to the e300 core. A second PLL inside the core multiplies up the
csb_clk frequency to create the internal clock for the core (core_clk). The system and core PLL multipliers
are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL) which is
loaded at power-on reset or by one of the hard-coded reset options.For more information, see the Reset
Configuration chapter in the MPC8306 PowerQUICC II Pro Communications Processor Reference
Manual.
The qe_clk frequency is determined by the QUICC Engine PLL multiplication factor (RCWL[CEPMF])
and the QUICC Engine PLL division factor (RCWL[CEPDF]) as the following equation:
qe_clk = (QE_CLK_IN × CEPMF)
(1 + CEPDF)
Eqn. 2
qe_clk = (QE_CLK_IN × CEPMF)
(1 + CEPDF)
Eqn. 3
For more information, see the QUICC Engine PLL Multiplication Factor section and the “QUICC Engine
PLL Division Factor” section in the MPC8306 PowerQUICC II Pro Communications Processor
Reference Manual for more information.
The DDR SDRAM memory controller operates with a frequency equal to twice the frequency of csb_clk.
Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider
(
2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate
is the same frequency as ddr_clk.
The local bus memory controller operates with a frequency equal to the frequency of csb_clk. Note that
lbc_clk is not the external local bus frequency; lbc_clk passes through the LBC clock divider to create the
external local bus clock outputs (LCLK). The LBC clock divider ratio is controlled by LCCR[CLKDIV].
For more information, see the LBC Bus Clock and Clock Ratios section in the MPC8306 PowerQUICC
II Pro Communications Processor Reference Manual.
相關(guān)PDF資料
PDF描述
MPC8306CVMACDCA 32-BIT, 200 MHz, RISC PROCESSOR, PBGA369
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC8306VMADDC 制造商:Freescale Semiconductor 功能描述:MPC8306VMADDC - Bulk
MPC8306VMADDCA 功能描述:微處理器 - MPU E300 MP 266 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8306VMADDCA 制造商:Freescale Semiconductor 功能描述:IC 32-BIT MPU 266 MHz 369-LFBGA
MPC8306VMAFDCA 功能描述:微處理器 - MPU E300 MP 333 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8308 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor
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