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| 型號： | MPC8308-SOM |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 19/83頁 |
| 文件大?。?/td> | 0K |
| 描述： | MODULE BOARD FOR MPC8308 |
| 標準包裝： | 1 |
| 系列： | PowerQUICC II™ PRO |
| 類型： | MPU |
| 適用于相關產(chǎn)品： | MPC8308 |
| 所含物品： | 板 |
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MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
26
Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
Common Mode Voltage, Vcm
The common mode voltage is equal to one-half of the sum of the voltages between each conductor
of a balanced interchange circuit and ground. In this example, for SerDes output,
Vcm_out =(VTXn +VTXn)/2 = (A + B) / 2, which is the arithmetic mean of the two complimentary
output voltages within a differential pair. In a system, the common mode voltage may often differ
from one component’s output to the other’s input. Sometimes, it may be even different between the
receiver input and driver output circuits within the same component. It is also referred as the DC
offset in some occasion.
Figure 15. Differential Voltage Definitions for Transmitter or Receiver
To illustrate these definitions using real values, consider the case of a current mode logic (CML)
transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing
that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD
or TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, since
the differential signaling environment is fully symmetrical, the transmitter output’s differential swing
(VOD) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges
between 500 mV and –500 mV, in other words, VOD is 500 mV in one phase and –500 mV in the other
phase. The peak differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p)
is 1000 mV p-p.
10.2
SerDes Reference Clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by
the corresponding SerDes lanes. The SerDes reference clocks input is SD_REF_CLK and SD_REF_CLK
for PCI Express.
The following sections describe the SerDes reference clock requirements and some application
information.
Differential Swing, VID or VOD = A – B
A Volts
B Volts
TXn or RXn
Differential Peak Voltage, VDIFFp = |A – B|
Differential Peak-Peak Voltage, VDIFFpp = 2*VDIFFp (not shown)
Vcm = (A + B) / 2
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