參數(shù)資料
型號(hào): MPC8313ECZQAGD
廠商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA516
封裝: 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, TEPBGAII-516
文件頁(yè)數(shù): 6/100頁(yè)
文件大?。?/td> 1247K
代理商: MPC8313ECZQAGD
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
13
RESET Initialization
5
RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the MPC8313E.
5.1
RESET DC Electrical Characteristics
Table 9 provides the DC electrical characteristics for the RESET pins.
5.2
RESET AC Electrical Characteristics
Table 10 provides the reset initialization AC timing specifications.
Table 9. RESET Pins DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
—2.1
NVDD +0.3
V
Input low voltage
VIL
–0.3
0.8
V
Input current
IIN
0 V
≤ VIN ≤ NVDD
—±5
μA
Output high voltage
VOH
IOH = –8.0 mA
2.4
V
Output low voltage
VOL
IOL = 8.0 mA
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
0.4
V
Table 10. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HRESET or SRESET (input) to activate reset flow
32
tPCI_SYNC_IN
1
Required assertion time of PORESET with stable clock and power applied to
SYS_CLK_IN when the device is in PCI host mode
32
tSYS_CLK_IN
2
Required assertion time of PORESET with stable clock and power applied to
PCI_SYNC_IN when the device is in PCI agent mode
32
tPCI_SYNC_IN
1
HRESET assertion (output)
512
tPCI_SYNC_IN
1
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:3]
and CFG_SYS_CLK_IN_DIV) with respect to negation of PORESET when
the device is in PCI host mode
4—
tSYS_CLK_IN
2
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2]
and CFG_CLKIN_DIV) with respect to negation of PORESET when the
device is in PCI agent mode
4—
tPCI_SYNC_IN
1
Input hold time for POR configuration signals with respect to negation of
HRESET
0—
ns
Time for the device to turn off POR configuration signal drivers with respect
to the assertion of HRESET
—4
ns
3
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