參數(shù)資料
型號(hào)： MPC8313VRAFFB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 333 MHz, MICROPROCESSOR, PBGA516
封裝： 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, LEAD FREE, TEPBGAII-516
文件頁數(shù)： 26/100頁
文件大?。?/td> 1247K
代理商： MPC8313VRAFFB
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
31
Ethernet: Three-Speed Ethernet, MII Management
8.3.4.1
SGMII Transmit AC Timing Specifications
Table 34 provides the SGMII transmit AC timing targets. A source synchronous clock is not provided.
8.3.4.2
SGMII Receive AC Timing Specifications
Table 35 provides the SGMII receive AC timing specifications. Source synchronous clocking is not
supported. Clock is recovered from the data. Figure 17 shows the SGMII receiver input compliance mask
eye diagram.
Table 34. SGMII Transmit AC Timing Specifications
At recommended operating conditions with XCOREVDD = 1.0 V ± 5%.
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Deterministic jitter
JD
—
0.17
UI p-p
Total jitter
JT
—
0.35
UI p-p
Unit interval
UI
799.92
800
800.08
ps
1
VOD fall time (80%–20%)
tfall
50
—
120
ps
VOD rise time (20%–80%)
trise
50
—
120
ps
Note:
1. Each UI is 800 ps ± 100 ppm.
Table 35. SGMII Receive AC Timing Specifications
At recommended operating conditions with XCOREVDD = 1.0 V ± 5%.
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Deterministic jitter tolerance
JD
0.37
—
UI p-p
1
Combined deterministic and random jitter tolerance
JDR
0.55
—
UI p-p
1
Sinusoidal jitter tolerance
JSIN
0.1
—
UI p-p
1
Total jitter tolerance
JT
0.65
—
UI p-p
1
Bit error ratio
BER
—
10–12
Unit interval
UI
799.92
800
800.08
ps
2
AC coupling capacitor
CTX
5—
200
nF
3
Notes:
1. Measured at receiver.
2. Each UI is 800 ps ± 100 ppm.
3. The external AC coupling capacitor is required. It is recommended to be placed near the device transmitter outputs.
4. Refer to the
RapidIO 1x/4x LP Serial Physical Layer Specification, for interpretation of jitter specifications.
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