參數(shù)資料
型號(hào): MPC8315VRADDA
廠商: Freescale Semiconductor
文件頁數(shù): 42/106頁
文件大小: 0K
描述: MPU POWERQUICC II PRO 620-PBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 266MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 620-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 620-PBGA(29x29)
包裝: 托盤
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
40
Freescale Semiconductor
USB
Figure 22 and Figure 23 provide the AC test load and signals for the USB, respectively.
Figure 22. USB AC Test Load
Figure 23. USB Signals
10.2
On-Chip USB PHY
This section provides the AC and DC electrical specifications for the USB PHY interface of the
MPC8315E.
For details refer to Tables 7-7 through 7-10, and Table 7-14 in the USB 2.0 Specifications document, and
the pull-up/down resistors ECN updates, all available at www.usb.org.
This table provides the USB clock input (USB_CLK_IN) DC timing specifications.
USB clock to output valid—all outputs
tUSKHOV
—9
ns
1
Output hold from USB clock—all outputs
tUSKHOX
1—
ns
1
Note:
1. The symbols used for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes USB timing
(US) for the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, tUSKHOX
symbolizes USB timing (US) for the us clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or
output hold time.
2. All timings are in reference to USB clock.
3. All signals are measured from NVDD/2 of the rising edge of USB clock to 0.4
NVDD of the signal in question for 3.3-V
signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through
the component pin is less than or equal to the leakage current specification.
Table 40. USB General Timing Parameters (continued)
Parameter
Symbol 1
Min
Max
Unit
Note
Output
Z0 = 50
NVDD/2
RL = 50
Output Signals
tUSKHOV
USBDR_CLK
Input Signals
tUSIXKH
tUSIVKH
tUSKHOX
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